Explicitly provide refClockFreqMHz to harnessClockInstantiator
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@@ -24,7 +24,7 @@ class WithArtyTweaks extends Config(
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new chipyard.harness.WithHarnessBinderClockFreqMHz(32) ++
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new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
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new chipyard.config.WithDTSTimebase(32768) ++
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new chipyard.config.WithDTSTimebase(32000) ++
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new chipyard.config.WithSystemBusFrequency(32) ++
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new chipyard.config.WithPeripheryBusFrequency(32) ++
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new testchipip.WithNoSerialTL
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@@ -21,6 +21,7 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
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def success = {require(false, "Success not supported"); false.B }
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def referenceClockFreqMHz = 32.0
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def referenceClock = clock_32MHz
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def referenceReset = hReset
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@@ -76,6 +76,7 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
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harnessSysPLL.plls.foreach(_._1.getReset.get := pllReset)
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def referenceClockFreqMHz = dutFreqMHz
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def referenceClock = dutClock.in.head._1.clock
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def referenceReset = dutClock.in.head._1.reset
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def success = { require(false, "Unused"); false.B }
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@@ -114,6 +114,7 @@ class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModul
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val hReset = Wire(Reset())
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hReset := _outer.dutClock.in.head._1.reset
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def referenceClockFreqMHz = _outer.dutFreqMHz
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def referenceClock = _outer.dutClock.in.head._1.clock
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def referenceReset = hReset
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def success = { require(false, "Unused"); false.B }
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@@ -118,6 +118,7 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod
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val hReset = Wire(Reset())
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hReset := _outer.dutClock.in.head._1.reset
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def referenceClockFreqMHz = _outer.dutFreqMHz
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def referenceClock = _outer.dutClock.in.head._1.clock
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def referenceReset = hReset
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def success = { require(false, "Unused"); false.B }
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