Explicitly provide refClockFreqMHz to harnessClockInstantiator

This commit is contained in:
Jerry Zhao
2023-05-13 11:18:03 -07:00
parent a89b86c785
commit 2077e4304d
10 changed files with 23 additions and 7 deletions

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@@ -24,7 +24,7 @@ class WithArtyTweaks extends Config(
new chipyard.harness.WithHarnessBinderClockFreqMHz(32) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.config.WithDTSTimebase(32768) ++
new chipyard.config.WithDTSTimebase(32000) ++
new chipyard.config.WithSystemBusFrequency(32) ++
new chipyard.config.WithPeripheryBusFrequency(32) ++
new testchipip.WithNoSerialTL

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@@ -21,6 +21,7 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
def success = {require(false, "Success not supported"); false.B }
def referenceClockFreqMHz = 32.0
def referenceClock = clock_32MHz
def referenceReset = hReset

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@@ -76,6 +76,7 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
harnessSysPLL.plls.foreach(_._1.getReset.get := pllReset)
def referenceClockFreqMHz = dutFreqMHz
def referenceClock = dutClock.in.head._1.clock
def referenceReset = dutClock.in.head._1.reset
def success = { require(false, "Unused"); false.B }

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@@ -114,6 +114,7 @@ class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModul
val hReset = Wire(Reset())
hReset := _outer.dutClock.in.head._1.reset
def referenceClockFreqMHz = _outer.dutFreqMHz
def referenceClock = _outer.dutClock.in.head._1.clock
def referenceReset = hReset
def success = { require(false, "Unused"); false.B }

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@@ -118,6 +118,7 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod
val hReset = Wire(Reset())
hReset := _outer.dutClock.in.head._1.reset
def referenceClockFreqMHz = _outer.dutFreqMHz
def referenceClock = _outer.dutClock.in.head._1.clock
def referenceReset = hReset
def success = { require(false, "Unused"); false.B }