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new tutorial make variables for ease of use

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Nayiri K
2022-09-16 00:24:46 -07:00
parent 7ad77358f8
commit 205adeef53
5 changed files with 334 additions and 119 deletions
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121
vlsi/example-sky130.yml
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@@ -6,12 +6,9 @@ vlsi.core.max_threads: 12
# Technology paths
technology.sky130:
# sky130A: "path-to-sky130A/"
sky130A: "path-to-sky130A/"
openram_lib: "path-to-sky130_sram_macros/"
sky130_nda: "path-to-skywater-src-nda/"
# openram_lib: "path-to-sky130_sram_macros/"
sky130A: "/tools/C/nayiri/sky130/sky130A"
# sky130_nda: "path-to-skywater-src-nda/"
openram_lib: "/tools/C/nayiri/sky130/sky130_sram_macros"
# General Hammer Inputs
@@ -51,120 +48,6 @@ par.generate_power_straps_options:
power_utilization_met4: 0.1
power_utilization_met5: 0.1
# Placement Constraints
vlsi.inputs.placement_constraints:
- path: "ChipTop"
type: toplevel
x: 0
y: 0
width: 3800
height: 2500
margins:
left: 0
right: 0
top: 0
bottom: 0
# # Place data cache SRAM instances
# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
# type: hardmacro
# x: 50
# y: 100
# orientation: r0
# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
# type: hardmacro
# x: 50
# y: 700
# orientation: r0
# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0"
# type: hardmacro
# x: 50
# y: 1300
# orientation: r0
# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0"
# type: hardmacro
# x: 50
# y: 1900
# orientation: r0
# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0"
# type: hardmacro
# x: 1000
# y: 1900
# orientation: r0
# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0"
# type: hardmacro
# x: 1000
# y: 1300
# orientation: r0
# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0"
# type: hardmacro
# x: 1000
# y: 700
# orientation: r0
# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0"
# type: hardmacro
# x: 1000
# y: 100
# orientation: r0
# # Place instruction cache SRAM instances
# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
# type: hardmacro
# x: 3700
# y: 100
# orientation: r0
# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0"
# type: hardmacro
# x: 3700
# y: 700
# orientation: r0
# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
# type: hardmacro
# x: 3000
# y: 100
# orientation: r0
# # Place L2 TLB SRAM instances
# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
# type: hardmacro
# x: 1900
# y: 1900
# orientation: "r0"
# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1"
# type: hardmacro
# x: 2600
# y: 1900
# orientation: "r0"
# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2"
# type: hardmacro
# x: 3300
# y: 1900
# orientation: "r0"
# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3"
# type: hardmacro
# x: 3950
# y: 1900
# orientation: "r0"
# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4"
# type: hardmacro
# x: 3950
# y: 1300
# orientation: "r0"
# Pin placement constraints
vlsi.inputs.pin_mode: generated
vlsi.inputs.pin.generate_mode: semi_auto