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Remove bringup vcu118

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This commit is contained in:
Jerry Zhao
2024-01-26 18:39:58 -08:00
parent 66deeee9a7
commit 205a1f2029
9 changed files with 14 additions and 549 deletions
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26
fpga/src/main/scala/arty100t/HarnessBinders.scala
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@@ -61,10 +61,10 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
harnessIO <> port.io
harnessIO match {
case io: DecoupledSerialIO => {
case io: DecoupledPhitIO => {
val clkIO = io match {
case io: InternalSyncSerialIO => IOPin(io.clock_out)
case io: ExternalSyncSerialIO => IOPin(io.clock_in)
case io: InternalSyncPhitIO => IOPin(io.clock_out)
case io: ExternalSyncPhitIO => IOPin(io.clock_in)
}
val packagePinsWithPackageIOs = Seq(
("G13", clkIO),
@@ -72,14 +72,14 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
("A11", IOPin(io.out.ready)),
("D12", IOPin(io.in.valid)),
("D13", IOPin(io.in.ready)),
("B18", IOPin(io.out.bits, 0)),
("A18", IOPin(io.out.bits, 1)),
("K16", IOPin(io.out.bits, 2)),
("E15", IOPin(io.out.bits, 3)),
("E16", IOPin(io.in.bits, 0)),
("D15", IOPin(io.in.bits, 1)),
("C15", IOPin(io.in.bits, 2)),
("J17", IOPin(io.in.bits, 3))
("B18", IOPin(io.out.bits.phit, 0)),
("A18", IOPin(io.out.bits.phit, 1)),
("K16", IOPin(io.out.bits.phit, 2)),
("E15", IOPin(io.out.bits.phit, 3)),
("E16", IOPin(io.in.bits.phit, 0)),
("D15", IOPin(io.in.bits.phit, 1)),
("C15", IOPin(io.in.bits.phit, 2)),
("J17", IOPin(io.in.bits.phit, 3))
)
packagePinsWithPackageIOs foreach { case (pin, io) => {
artyTh.xdc.addPackagePin(io, pin)
@@ -88,10 +88,10 @@ class WithArty100TSerialTLToGPIO extends HarnessBinder({
// Don't add IOB to the clock, if its an input
io match {
case io: InternalSyncSerialIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
case io: InternalSyncPhitIO => packagePinsWithPackageIOs foreach { case (pin, io) => {
artyTh.xdc.addIOB(io)
}}
case io: ExternalSyncSerialIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
case io: ExternalSyncPhitIO => packagePinsWithPackageIOs.drop(1).foreach { case (pin, io) => {
artyTh.xdc.addIOB(io)
}}
}