undid some makefile changes
This commit is contained in:
Nayiri K
@@ -34,10 +34,9 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
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* All of the elaborated Chisel and FIRRTL.
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* ``hammer``, ``hammer-<vendor>-plugins``, ``hammer-<tech>-plugin``
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* ``hammer``, ``hammer/src/hammer-vlsi/<syn-par-drc-lvs>/<tool>``, ``hammer/src/hammer-vlsi/technology/<tech>``
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* Core repository, and commercial tool and NDA technology plugins.
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* Open-source plugins are located under ``hammer/src/hammer-vlsi/<syn-par-drc-lvs>/<tool>`` and ``hammer/src/hammer-vlsi/technology/<tech>``
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* Core repository, and open-source tool and technology plugins.
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Prerequisites
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-------------
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@@ -75,6 +74,15 @@ Pull the Hammer environment into the shell:
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Running the VLSI Flow
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---------------------
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For this tutorial we will be setting the Make variable ``tutorial=sky130-openroad`` to abbreviate the configuration.
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The current options for this variable are defined in ``tutorial.mk``, a few of which are summarized as follows:
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* ``CONFIG=TinyRocketConfig`` selects the ``TinyRocketConfig`` from the Chipyard configurations.
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* ``tech_name`` sets a few more necessary paths in the ``Makefile``, such as the appropriate Hammer plugin
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* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-openroad.yml`` and ``example-sky130.yml``, which are described below
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* ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml``
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* ``VLSI_OBJ_DIR`` gives the build directory a unique name to allow running multiple flows in the same repo.
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example-vlsi-sky130
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^^^^^^^^^^^^^^^^^^^
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This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow.
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@@ -102,7 +110,7 @@ To map the generic memory macros in the generarted Verilog to the SRAMs in your
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.. code-block:: shell
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make srams tech_name=sky130 CONFIG=TinyRocketConfig
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make srams tutorial=sky130-openroad
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Generating Verilog
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^^^^^^^^^^^^^^^^^^
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@@ -110,7 +118,7 @@ To elaborate the ``TinyRocketConfig`` from Chisel to Verilog, run:
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.. code-block:: shell
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make verilog tech_name=sky130 CONFIG=TinyRocketConfig
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make verilog tutorial=sky130-openroad
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The ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime. The resulting verilog is located in ``./generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.v``.
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@@ -135,7 +143,7 @@ Synthesis
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.. code-block:: shell
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make syn tech_name=sky130 CONFIG=TinyRocketConfig
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make syn tutorial=sky130-openroad
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Post-synthesis logs and collateral are in ``build/syn-rundir``.
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@@ -145,7 +153,7 @@ Place-and-Route
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^^^^^^^^^^^^^^^
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.. code-block:: shell
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make par tech_name=sky130 CONFIG=TinyRocketConfig
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make par tutorial=sky130-openroad
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After completion, the final database can be opened in an interactive OpenROAD session.
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@@ -174,8 +182,8 @@ To run DRC & LVS:
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.. code-block:: shell
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make drc tech_name=sky130 CONFIG=TinyRocketConfig
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make lvs tech_name=sky130 CONFIG=TinyRocketConfig
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make drc tutorial=sky130-openroad
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make lvs tutorial=sky130-openroad
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Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the
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`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__.
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224
vlsi/Makefile
224
vlsi/Makefile
@@ -28,15 +28,15 @@ SMEMS_CACHE ?= $(tech_dir)/sram-cache.json
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SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json
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ifdef USE_SRAM_COMPILER
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MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict
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MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict
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else
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MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict
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MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict
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endif
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ENV_YML ?= $(vlsi_dir)/env.yml
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TECH_CONF ?= $(if $(filter $(tech_name),nangate45), example-nangate45.yml,\
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$(if $(filter $(tech_name),asap7), example-asap7.yml,\
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example-sky130.yml))
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TECH_CONF ?= $(if $(filter $(tech_name),nangate45), example-nangate45.yml,\
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$(if $(filter $(tech_name),asap7), example-asap7.yml,\
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example-sky130.yml))
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TOOLS_CONF ?= example-tools.yml
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INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF)
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HAMMER_EXEC ?= $(if $(filter $(tech_name),sky130),\
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@@ -47,9 +47,9 @@ VLSI_HARNESS_DUT_NAME ?= chiptop
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# If overriding, this should be relative to $(vlsi_dir)
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VLSI_OBJ_DIR ?= build
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ifneq ($(CUSTOM_VLOG),)
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OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/custom-$(VLSI_TOP)
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OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/custom-$(VLSI_TOP)
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else
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OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP)
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OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP)
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endif
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#########################################################################################
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@@ -58,11 +58,11 @@ endif
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ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE)
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extra_v_includes = $(build_dir)/EICG_wrapper.v
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ifneq ($(CUSTOM_VLOG), )
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VLSI_RTL = $(CUSTOM_VLOG)
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VLSI_BB = /dev/null
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VLSI_RTL = $(CUSTOM_VLOG)
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VLSI_BB = /dev/null
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else
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VLSI_RTL = $(ALL_RTL) $(extra_v_includes)
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VLSI_BB = $(sim_top_blackboxes)
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VLSI_RTL = $(ALL_RTL) $(extra_v_includes)
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VLSI_BB = $(sim_top_blackboxes)
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endif
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.PHONY: default verilog
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@@ -92,13 +92,13 @@ sram_generator: $(SRAM_CONF)
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$(SMEMS_HAMMER): $(TOP_SMEMS_FILE)
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$(SRAM_GENERATOR_CONF): $(SMEMS_HAMMER)
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mkdir -p $(dir $@)
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echo "vlsi.inputs.sram_parameters: '$(SMEMS_HAMMER)'" >> $@
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echo "vlsi.inputs.sram_parameters_meta: [\"transclude\", \"json2list\"]">> $@
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mkdir -p $(dir $@)
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echo "vlsi.inputs.sram_parameters: '$(SMEMS_HAMMER)'" >> $@
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echo "vlsi.inputs.sram_parameters_meta: [\"transclude\", \"json2list\"]">> $@
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$(SRAM_CONF): $(SRAM_GENERATOR_CONF)
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cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator
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cd $(vlsi_dir) && cp output.json $@
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cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator
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cd $(vlsi_dir) && cp output.json $@
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#########################################################################################
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# simulation input configuration
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@@ -106,16 +106,16 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF)
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include $(base_dir)/vcs.mk
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SIM_FILE_REQS += \
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$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
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$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
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# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir)
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$(sim_files): $(SIM_FILE_REQS) | $(build_dir)
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cp -f $^ $(build_dir)
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$(foreach file,\
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$^,\
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$(if $(filter %.h,$(file)),\
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,\
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echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
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cp -f $^ $(build_dir)
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$(foreach file,\
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$^,\
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$(if $(filter %.h,$(file)),\
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,\
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echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
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SIM_CONF = $(OBJ_DIR)/sim-inputs.yml
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SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml
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@@ -123,97 +123,97 @@ SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml
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include $(vlsi_dir)/sim.mk
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$(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) $(dramsim_lib)
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mkdir -p $(dir $@)
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echo "sim.inputs:" > $@
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echo " top_module: $(VLSI_TOP)" >> $@
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echo " input_files:" >> $@
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for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " input_files_meta: 'append'" >> $@
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echo " timescale: '1ns/10ps'" >> $@
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echo " options:" >> $@
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for x in $(VCS_NONCC_OPTS); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " options_meta: 'append'" >> $@
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echo " defines:" >> $@
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for x in $(subst +define+,,$(PREPROC_DEFINES)); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " defines_meta: 'append'" >> $@
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echo " compiler_cc_opts:" >> $@
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for x in $(filter-out "",$(VCS_CXXFLAGS)); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " compiler_cc_opts_meta: 'append'" >> $@
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echo " compiler_ld_opts:" >> $@
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for x in $(filter-out "",$(VCS_LDFLAGS)); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " compiler_ld_opts_meta: 'append'" >> $@
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echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@
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echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@
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echo " execution_flags:" >> $@
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for x in $(SIM_FLAGS); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " execution_flags_meta: 'append'" >> $@
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mkdir -p $(dir $@)
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echo "sim.inputs:" > $@
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echo " top_module: $(VLSI_TOP)" >> $@
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echo " input_files:" >> $@
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for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " input_files_meta: 'append'" >> $@
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echo " timescale: '1ns/10ps'" >> $@
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echo " options:" >> $@
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for x in $(VCS_NONCC_OPTS); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " options_meta: 'append'" >> $@
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echo " defines:" >> $@
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for x in $(subst +define+,,$(PREPROC_DEFINES)); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " defines_meta: 'append'" >> $@
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echo " compiler_cc_opts:" >> $@
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for x in $(filter-out "",$(VCS_CXXFLAGS)); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " compiler_cc_opts_meta: 'append'" >> $@
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echo " compiler_ld_opts:" >> $@
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for x in $(filter-out "",$(VCS_LDFLAGS)); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " compiler_ld_opts_meta: 'append'" >> $@
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echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@
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echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@
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echo " execution_flags:" >> $@
|
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for x in $(SIM_FLAGS); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " execution_flags_meta: 'append'" >> $@
|
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ifneq ($(BINARY), )
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echo " benchmarks: ['$(BINARY)']" >> $@
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echo " benchmarks: ['$(BINARY)']" >> $@
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endif
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echo " tb_dut: 'TestDriver.testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@
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echo " tb_dut: 'TestDriver.testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@
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$(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
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mkdir -p $(dir $@)
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mkdir -p $(output_dir)
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echo "sim.inputs:" > $@
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echo " defines: ['DEBUG']" >> $@
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echo " defines_meta: 'append'" >> $@
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echo " execution_flags:" >> $@
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for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " execution_flags_meta: 'append'" >> $@
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echo " saif.mode: 'time'" >> $@
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echo " saif.start_time: '0ns'" >> $@
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echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
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mkdir -p $(dir $@)
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mkdir -p $(output_dir)
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echo "sim.inputs:" > $@
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echo " defines: ['DEBUG']" >> $@
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echo " defines_meta: 'append'" >> $@
|
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echo " execution_flags:" >> $@
|
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for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \
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echo ' - "'$$x'"' >> $@; \
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done
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echo " execution_flags_meta: 'append'" >> $@
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echo " saif.mode: 'time'" >> $@
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echo " saif.start_time: '0ns'" >> $@
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echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
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ifdef USE_FSDB
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echo " options:" >> $@
|
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echo ' - "-kdb"' >> $@
|
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echo " options_meta: 'append'" >> $@
|
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echo "sim.outputs.waveforms: ['$(sim_out_name).fsdb']" >> $@
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echo " options:" >> $@
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echo ' - "-kdb"' >> $@
|
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echo " options_meta: 'append'" >> $@
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echo "sim.outputs.waveforms: ['$(sim_out_name).fsdb']" >> $@
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else
|
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echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@
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echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@
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endif
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|
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$(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
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mkdir -p $(dir $@)
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echo "sim.inputs:" > $@
|
||||
echo " defines: ['NTC']" >> $@
|
||||
echo " defines_meta: 'append'" >> $@
|
||||
echo " timing_annotated: 'true'" >> $@
|
||||
mkdir -p $(dir $@)
|
||||
echo "sim.inputs:" > $@
|
||||
echo " defines: ['NTC']" >> $@
|
||||
echo " defines_meta: 'append'" >> $@
|
||||
echo " timing_annotated: 'true'" >> $@
|
||||
|
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POWER_CONF = $(OBJ_DIR)/power-inputs.yml
|
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include $(vlsi_dir)/power.mk
|
||||
$(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
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||||
mkdir -p $(dir $@)
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||||
echo "power.inputs:" > $@
|
||||
echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@
|
||||
echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@
|
||||
mkdir -p $(dir $@)
|
||||
echo "power.inputs:" > $@
|
||||
echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@
|
||||
echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@
|
||||
ifneq ($(BINARY), )
|
||||
echo " waveforms: [" >> $@
|
||||
echo " waveforms: [" >> $@
|
||||
ifdef USE_FSDB
|
||||
echo " '$(sim_out_name).fsdb'" >> $@
|
||||
echo " '$(sim_out_name).fsdb'" >> $@
|
||||
else
|
||||
echo " '$(sim_out_name).vpd'" >> $@
|
||||
echo " '$(sim_out_name).vpd'" >> $@
|
||||
endif
|
||||
echo " ]" >> $@
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||||
echo " ]" >> $@
|
||||
endif
|
||||
echo " start_times: ['0ns']" >> $@
|
||||
echo " end_times: [" >> $@
|
||||
echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
|
||||
echo " ]" >> $@
|
||||
echo " start_times: ['0ns']" >> $@
|
||||
echo " end_times: [" >> $@
|
||||
echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
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||||
echo " ]" >> $@
|
||||
|
||||
#########################################################################################
|
||||
# synthesis input configuration
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||||
@@ -221,23 +221,23 @@ endif
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||||
SYN_CONF = $(OBJ_DIR)/inputs.yml
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||||
GENERATED_CONFS = $(SYN_CONF)
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||||
ifeq ($(CUSTOM_VLOG), )
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||||
GENERATED_CONFS += $(SRAM_CONF)
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||||
GENERATED_CONFS += $(SRAM_CONF)
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||||
endif
|
||||
|
||||
$(SYN_CONF): $(VLSI_RTL) $(VLSI_BB)
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||||
mkdir -p $(dir $@)
|
||||
echo "sim.inputs:" > $@
|
||||
echo " input_files:" >> $@
|
||||
for x in $(VLSI_RTL); do \
|
||||
echo ' - "'$$x'"' >> $@; \
|
||||
done
|
||||
echo " input_files_meta: 'append'" >> $@
|
||||
echo "synthesis.inputs:" >> $@
|
||||
echo " top_module: $(VLSI_TOP)" >> $@
|
||||
echo " input_files:" >> $@
|
||||
for x in $(VLSI_RTL) $(shell cat $(VLSI_BB)); do \
|
||||
echo ' - "'$$x'"' >> $@; \
|
||||
done
|
||||
mkdir -p $(dir $@)
|
||||
echo "sim.inputs:" > $@
|
||||
echo " input_files:" >> $@
|
||||
for x in $(VLSI_RTL); do \
|
||||
echo ' - "'$$x'"' >> $@; \
|
||||
done
|
||||
echo " input_files_meta: 'append'" >> $@
|
||||
echo "synthesis.inputs:" >> $@
|
||||
echo " top_module: $(VLSI_TOP)" >> $@
|
||||
echo " input_files:" >> $@
|
||||
for x in $(VLSI_RTL) $(shell cat $(VLSI_BB)); do \
|
||||
echo ' - "'$$x'"' >> $@; \
|
||||
done
|
||||
|
||||
#########################################################################################
|
||||
# AUTO BUILD FLOW
|
||||
@@ -249,7 +249,7 @@ buildfile: $(OBJ_DIR)/hammer.d
|
||||
# TODO: make this dependency smarter so that we don't need this at all
|
||||
HAMMER_D_DEPS ?= $(GENERATED_CONFS)
|
||||
$(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS)
|
||||
$(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(GENERATED_CONFS), -p $(x)) --obj_dir $(OBJ_DIR) build
|
||||
$(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(GENERATED_CONFS), -p $(x)) --obj_dir $(OBJ_DIR) build
|
||||
|
||||
-include $(OBJ_DIR)/hammer.d
|
||||
|
||||
@@ -258,4 +258,4 @@ $(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS)
|
||||
#########################################################################################
|
||||
.PHONY: clean
|
||||
clean:
|
||||
rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF)
|
||||
rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF)
|
||||
|
||||
Reference in New Issue
Block a user