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undid some makefile changes

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This commit is contained in:
Nayiri K
2022-09-27 14:12:53 -07:00
parent be7bf0ed5b
commit 205895e452
2 changed files with 130 additions and 122 deletions
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26
docs/VLSI/Sky130-OpenROAD-Tutorial.rst
View File

@@ -34,10 +34,9 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo
* All of the elaborated Chisel and FIRRTL. * All of the elaborated Chisel and FIRRTL.
* ``hammer``, ``hammer-<vendor>-plugins``, ``hammer-<tech>-plugin`` * ``hammer``, ``hammer/src/hammer-vlsi/<syn-par-drc-lvs>/<tool>``, ``hammer/src/hammer-vlsi/technology/<tech>``
* Core repository, and commercial tool and NDA technology plugins. * Core repository, and open-source tool and technology plugins.
* Open-source plugins are located under ``hammer/src/hammer-vlsi/<syn-par-drc-lvs>/<tool>`` and ``hammer/src/hammer-vlsi/technology/<tech>``
Prerequisites Prerequisites
------------- -------------
@@ -75,6 +74,15 @@ Pull the Hammer environment into the shell:
Running the VLSI Flow Running the VLSI Flow
--------------------- ---------------------
For this tutorial we will be setting the Make variable ``tutorial=sky130-openroad`` to abbreviate the configuration.
The current options for this variable are defined in ``tutorial.mk``, a few of which are summarized as follows:
* ``CONFIG=TinyRocketConfig`` selects the ``TinyRocketConfig`` from the Chipyard configurations.
* ``tech_name`` sets a few more necessary paths in the ``Makefile``, such as the appropriate Hammer plugin
* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-openroad.yml`` and ``example-sky130.yml``, which are described below
* ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml``
* ``VLSI_OBJ_DIR`` gives the build directory a unique name to allow running multiple flows in the same repo.
example-vlsi-sky130 example-vlsi-sky130
^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^
This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow.
@@ -102,7 +110,7 @@ To map the generic memory macros in the generarted Verilog to the SRAMs in your
.. code-block:: shell .. code-block:: shell
make srams tech_name=sky130 CONFIG=TinyRocketConfig make srams tutorial=sky130-openroad
Generating Verilog Generating Verilog
^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^
@@ -110,7 +118,7 @@ To elaborate the ``TinyRocketConfig`` from Chisel to Verilog, run:
.. code-block:: shell .. code-block:: shell
make verilog tech_name=sky130 CONFIG=TinyRocketConfig make verilog tutorial=sky130-openroad
The ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime. The resulting verilog is located in ``./generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.v``. The ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime. The resulting verilog is located in ``./generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.v``.
@@ -135,7 +143,7 @@ Synthesis
.. code-block:: shell .. code-block:: shell
make syn tech_name=sky130 CONFIG=TinyRocketConfig make syn tutorial=sky130-openroad
Post-synthesis logs and collateral are in ``build/syn-rundir``. Post-synthesis logs and collateral are in ``build/syn-rundir``.
@@ -145,7 +153,7 @@ Place-and-Route
^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^
.. code-block:: shell .. code-block:: shell
make par tech_name=sky130 CONFIG=TinyRocketConfig make par tutorial=sky130-openroad
After completion, the final database can be opened in an interactive OpenROAD session. After completion, the final database can be opened in an interactive OpenROAD session.
@@ -174,8 +182,8 @@ To run DRC & LVS:
.. code-block:: shell .. code-block:: shell
make drc tech_name=sky130 CONFIG=TinyRocketConfig make drc tutorial=sky130-openroad
make lvs tech_name=sky130 CONFIG=TinyRocketConfig make lvs tutorial=sky130-openroad
Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the
`Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__. `Sky130 Hammer plugin README <https://github.com/ucb-bar/hammer/blob/master/src/hammer-vlsi/technology/sky130/README.md>`__.

226
vlsi/Makefile
View File

@@ -28,15 +28,15 @@ SMEMS_CACHE ?= $(tech_dir)/sram-cache.json
SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json
ifdef USE_SRAM_COMPILER ifdef USE_SRAM_COMPILER
MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict
else else
MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict
endif endif
ENV_YML ?= $(vlsi_dir)/env.yml ENV_YML ?= $(vlsi_dir)/env.yml
TECH_CONF ?= $(if $(filter $(tech_name),nangate45), example-nangate45.yml,\ TECH_CONF ?= $(if $(filter $(tech_name),nangate45), example-nangate45.yml,\
$(if $(filter $(tech_name),asap7), example-asap7.yml,\ $(if $(filter $(tech_name),asap7), example-asap7.yml,\
example-sky130.yml)) example-sky130.yml))
TOOLS_CONF ?= example-tools.yml TOOLS_CONF ?= example-tools.yml
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF)
HAMMER_EXEC ?= $(if $(filter $(tech_name),sky130),\ HAMMER_EXEC ?= $(if $(filter $(tech_name),sky130),\
@@ -47,9 +47,9 @@ VLSI_HARNESS_DUT_NAME ?= chiptop
# If overriding, this should be relative to $(vlsi_dir) # If overriding, this should be relative to $(vlsi_dir)
VLSI_OBJ_DIR ?= build VLSI_OBJ_DIR ?= build
ifneq ($(CUSTOM_VLOG),) ifneq ($(CUSTOM_VLOG),)
OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/custom-$(VLSI_TOP) OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/custom-$(VLSI_TOP)
else else
OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP) OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP)
endif endif
######################################################################################### #########################################################################################
@@ -58,11 +58,11 @@ endif
ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE) ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE)
extra_v_includes = $(build_dir)/EICG_wrapper.v extra_v_includes = $(build_dir)/EICG_wrapper.v
ifneq ($(CUSTOM_VLOG), ) ifneq ($(CUSTOM_VLOG), )
VLSI_RTL = $(CUSTOM_VLOG) VLSI_RTL = $(CUSTOM_VLOG)
VLSI_BB = /dev/null VLSI_BB = /dev/null
else else
VLSI_RTL = $(ALL_RTL) $(extra_v_includes) VLSI_RTL = $(ALL_RTL) $(extra_v_includes)
VLSI_BB = $(sim_top_blackboxes) VLSI_BB = $(sim_top_blackboxes)
endif endif
.PHONY: default verilog .PHONY: default verilog
@@ -92,13 +92,13 @@ sram_generator: $(SRAM_CONF)
$(SMEMS_HAMMER): $(TOP_SMEMS_FILE) $(SMEMS_HAMMER): $(TOP_SMEMS_FILE)
$(SRAM_GENERATOR_CONF): $(SMEMS_HAMMER) $(SRAM_GENERATOR_CONF): $(SMEMS_HAMMER)
mkdir -p $(dir $@) mkdir -p $(dir $@)
echo "vlsi.inputs.sram_parameters: '$(SMEMS_HAMMER)'" >> $@ echo "vlsi.inputs.sram_parameters: '$(SMEMS_HAMMER)'" >> $@
echo "vlsi.inputs.sram_parameters_meta: [\"transclude\", \"json2list\"]">> $@ echo "vlsi.inputs.sram_parameters_meta: [\"transclude\", \"json2list\"]">> $@
$(SRAM_CONF): $(SRAM_GENERATOR_CONF) $(SRAM_CONF): $(SRAM_GENERATOR_CONF)
cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator
cd $(vlsi_dir) && cp output.json $@ cd $(vlsi_dir) && cp output.json $@
######################################################################################### #########################################################################################
# simulation input configuration # simulation input configuration
@@ -106,16 +106,16 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF)
include $(base_dir)/vcs.mk include $(base_dir)/vcs.mk
SIM_FILE_REQS += \ SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
# copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir) # copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir)
$(sim_files): $(SIM_FILE_REQS) | $(build_dir) $(sim_files): $(SIM_FILE_REQS) | $(build_dir)
cp -f $^ $(build_dir) cp -f $^ $(build_dir)
$(foreach file,\ $(foreach file,\
$^,\ $^,\
$(if $(filter %.h,$(file)),\ $(if $(filter %.h,$(file)),\
,\ ,\
echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;)) echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
SIM_CONF = $(OBJ_DIR)/sim-inputs.yml SIM_CONF = $(OBJ_DIR)/sim-inputs.yml
SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml
@@ -123,97 +123,97 @@ SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml
include $(vlsi_dir)/sim.mk include $(vlsi_dir)/sim.mk
$(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) $(dramsim_lib) $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) $(dramsim_lib)
mkdir -p $(dir $@) mkdir -p $(dir $@)
echo "sim.inputs:" > $@ echo "sim.inputs:" > $@
echo " top_module: $(VLSI_TOP)" >> $@ echo " top_module: $(VLSI_TOP)" >> $@
echo " input_files:" >> $@ echo " input_files:" >> $@
for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \ for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \
echo ' - "'$$x'"' >> $@; \ echo ' - "'$$x'"' >> $@; \
done done
echo " input_files_meta: 'append'" >> $@ echo " input_files_meta: 'append'" >> $@
echo " timescale: '1ns/10ps'" >> $@ echo " timescale: '1ns/10ps'" >> $@
echo " options:" >> $@ echo " options:" >> $@
for x in $(VCS_NONCC_OPTS); do \ for x in $(VCS_NONCC_OPTS); do \
echo ' - "'$$x'"' >> $@; \ echo ' - "'$$x'"' >> $@; \
done done
echo " options_meta: 'append'" >> $@ echo " options_meta: 'append'" >> $@
echo " defines:" >> $@ echo " defines:" >> $@
for x in $(subst +define+,,$(PREPROC_DEFINES)); do \ for x in $(subst +define+,,$(PREPROC_DEFINES)); do \
echo ' - "'$$x'"' >> $@; \ echo ' - "'$$x'"' >> $@; \
done done
echo " defines_meta: 'append'" >> $@ echo " defines_meta: 'append'" >> $@
echo " compiler_cc_opts:" >> $@ echo " compiler_cc_opts:" >> $@
for x in $(filter-out "",$(VCS_CXXFLAGS)); do \ for x in $(filter-out "",$(VCS_CXXFLAGS)); do \
echo ' - "'$$x'"' >> $@; \ echo ' - "'$$x'"' >> $@; \
done done
echo " compiler_cc_opts_meta: 'append'" >> $@ echo " compiler_cc_opts_meta: 'append'" >> $@
echo " compiler_ld_opts:" >> $@ echo " compiler_ld_opts:" >> $@
for x in $(filter-out "",$(VCS_LDFLAGS)); do \ for x in $(filter-out "",$(VCS_LDFLAGS)); do \
echo ' - "'$$x'"' >> $@; \ echo ' - "'$$x'"' >> $@; \
done done
echo " compiler_ld_opts_meta: 'append'" >> $@ echo " compiler_ld_opts_meta: 'append'" >> $@
echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@
echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@
echo " execution_flags:" >> $@ echo " execution_flags:" >> $@
for x in $(SIM_FLAGS); do \ for x in $(SIM_FLAGS); do \
echo ' - "'$$x'"' >> $@; \ echo ' - "'$$x'"' >> $@; \
done done
echo " execution_flags_meta: 'append'" >> $@ echo " execution_flags_meta: 'append'" >> $@
ifneq ($(BINARY), ) ifneq ($(BINARY), )
echo " benchmarks: ['$(BINARY)']" >> $@ echo " benchmarks: ['$(BINARY)']" >> $@
endif endif
echo " tb_dut: 'TestDriver.testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@ echo " tb_dut: 'TestDriver.testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@
$(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
mkdir -p $(dir $@) mkdir -p $(dir $@)
mkdir -p $(output_dir) mkdir -p $(output_dir)
echo "sim.inputs:" > $@ echo "sim.inputs:" > $@
echo " defines: ['DEBUG']" >> $@ echo " defines: ['DEBUG']" >> $@
echo " defines_meta: 'append'" >> $@ echo " defines_meta: 'append'" >> $@
echo " execution_flags:" >> $@ echo " execution_flags:" >> $@
for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \ for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \
echo ' - "'$$x'"' >> $@; \ echo ' - "'$$x'"' >> $@; \
done done
echo " execution_flags_meta: 'append'" >> $@ echo " execution_flags_meta: 'append'" >> $@
echo " saif.mode: 'time'" >> $@ echo " saif.mode: 'time'" >> $@
echo " saif.start_time: '0ns'" >> $@ echo " saif.start_time: '0ns'" >> $@
echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@ echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
ifdef USE_FSDB ifdef USE_FSDB
echo " options:" >> $@ echo " options:" >> $@
echo ' - "-kdb"' >> $@ echo ' - "-kdb"' >> $@
echo " options_meta: 'append'" >> $@ echo " options_meta: 'append'" >> $@
echo "sim.outputs.waveforms: ['$(sim_out_name).fsdb']" >> $@ echo "sim.outputs.waveforms: ['$(sim_out_name).fsdb']" >> $@
else else
echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@ echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@
endif endif
$(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) $(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
mkdir -p $(dir $@) mkdir -p $(dir $@)
echo "sim.inputs:" > $@ echo "sim.inputs:" > $@
echo " defines: ['NTC']" >> $@ echo " defines: ['NTC']" >> $@
echo " defines_meta: 'append'" >> $@ echo " defines_meta: 'append'" >> $@
echo " timing_annotated: 'true'" >> $@ echo " timing_annotated: 'true'" >> $@
POWER_CONF = $(OBJ_DIR)/power-inputs.yml POWER_CONF = $(OBJ_DIR)/power-inputs.yml
include $(vlsi_dir)/power.mk include $(vlsi_dir)/power.mk
$(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) $(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files)
mkdir -p $(dir $@) mkdir -p $(dir $@)
echo "power.inputs:" > $@ echo "power.inputs:" > $@
echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@ echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@
echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@ echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@
ifneq ($(BINARY), ) ifneq ($(BINARY), )
echo " waveforms: [" >> $@ echo " waveforms: [" >> $@
ifdef USE_FSDB ifdef USE_FSDB
echo " '$(sim_out_name).fsdb'" >> $@ echo " '$(sim_out_name).fsdb'" >> $@
else else
echo " '$(sim_out_name).vpd'" >> $@ echo " '$(sim_out_name).vpd'" >> $@
endif endif
echo " ]" >> $@ echo " ]" >> $@
endif endif
echo " start_times: ['0ns']" >> $@ echo " start_times: ['0ns']" >> $@
echo " end_times: [" >> $@ echo " end_times: [" >> $@
echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@ echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
echo " ]" >> $@ echo " ]" >> $@
######################################################################################### #########################################################################################
# synthesis input configuration # synthesis input configuration
@@ -221,23 +221,23 @@ endif
SYN_CONF = $(OBJ_DIR)/inputs.yml SYN_CONF = $(OBJ_DIR)/inputs.yml
GENERATED_CONFS = $(SYN_CONF) GENERATED_CONFS = $(SYN_CONF)
ifeq ($(CUSTOM_VLOG), ) ifeq ($(CUSTOM_VLOG), )
GENERATED_CONFS += $(SRAM_CONF) GENERATED_CONFS += $(SRAM_CONF)
endif endif
$(SYN_CONF): $(VLSI_RTL) $(VLSI_BB) $(SYN_CONF): $(VLSI_RTL) $(VLSI_BB)
mkdir -p $(dir $@) mkdir -p $(dir $@)
echo "sim.inputs:" > $@ echo "sim.inputs:" > $@
echo " input_files:" >> $@ echo " input_files:" >> $@
for x in $(VLSI_RTL); do \ for x in $(VLSI_RTL); do \
echo ' - "'$$x'"' >> $@; \ echo ' - "'$$x'"' >> $@; \
done done
echo " input_files_meta: 'append'" >> $@ echo " input_files_meta: 'append'" >> $@
echo "synthesis.inputs:" >> $@ echo "synthesis.inputs:" >> $@
echo " top_module: $(VLSI_TOP)" >> $@ echo " top_module: $(VLSI_TOP)" >> $@
echo " input_files:" >> $@ echo " input_files:" >> $@
for x in $(VLSI_RTL) $(shell cat $(VLSI_BB)); do \ for x in $(VLSI_RTL) $(shell cat $(VLSI_BB)); do \
echo ' - "'$$x'"' >> $@; \ echo ' - "'$$x'"' >> $@; \
done done
######################################################################################### #########################################################################################
# AUTO BUILD FLOW # AUTO BUILD FLOW
@@ -249,7 +249,7 @@ buildfile: $(OBJ_DIR)/hammer.d
# TODO: make this dependency smarter so that we don't need this at all # TODO: make this dependency smarter so that we don't need this at all
HAMMER_D_DEPS ?= $(GENERATED_CONFS) HAMMER_D_DEPS ?= $(GENERATED_CONFS)
$(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS) $(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS)
$(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(GENERATED_CONFS), -p $(x)) --obj_dir $(OBJ_DIR) build $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(GENERATED_CONFS), -p $(x)) --obj_dir $(OBJ_DIR) build
-include $(OBJ_DIR)/hammer.d -include $(OBJ_DIR)/hammer.d
@@ -258,4 +258,4 @@ $(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS)
######################################################################################### #########################################################################################
.PHONY: clean .PHONY: clean
clean: clean:
rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF) rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF)