From 200fec07e67f00b234f0df17fc3828caf386092d Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Tue, 10 Sep 2019 11:09:44 -0700 Subject: [PATCH] make purpose of CachelessRocketConfig clearer --- docs/Customization/Memory-Hierarchy.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst index 967ae15b..4295ab15 100644 --- a/docs/Customization/Memory-Hierarchy.rst +++ b/docs/Customization/Memory-Hierarchy.rst @@ -63,6 +63,9 @@ The Broadcast Hub If you do not want to use the L2 cache (say, for a resource-limited embedded design), you can create a configuration without it. Instead of using the L2 cache, you will instead use RocketChip's TileLink broadcast hub. +To make such a configuration, you can just copy the definition of +``RocketConfig`` but omit the ``WithInclusiveCache`` mixin from the +list of included mixims. .. code-block:: scala