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Style/Comments from review of #35

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This commit is contained in:
John Wright
2019-02-13 10:02:34 -08:00
committed by John Wright
parent efd2f09b21
commit 1f58ea1e14
4 changed files with 12 additions and 9 deletions
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7
macros/src/main/scala/MacroCompiler.scala
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@@ -755,10 +755,9 @@ object MacroCompiler extends App {
def run(args: List[String]) { def run(args: List[String]) {
val (params, costParams, forcedMemories) = parseArgs(Map[MacroParam, String](), Map[String, String](), (Set.empty, Set.empty), args) val (params, costParams, forcedMemories) = parseArgs(Map[MacroParam, String](), Map[String, String](), (Set.empty, Set.empty), args)
try { try {
val macros = if (params.get(MacrosFormat) == Some("conf")) { val macros = params.get(MacrosFormat) match {
Utils.filterForSRAM(Utils.readConfFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox) case Some("conf") => Utils.filterForSRAM(Utils.readConfFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox)
} else { case _ => Utils.filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox)
Utils.filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox)
} }
if (macros.nonEmpty) { if (macros.nonEmpty) {

6
macros/src/main/scala/MemConf.scala
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@@ -8,13 +8,13 @@ sealed abstract class MemPort(val name: String) { override def toString = name }
case object ReadPort extends MemPort("read") case object ReadPort extends MemPort("read")
case object WritePort extends MemPort("write") case object WritePort extends MemPort("write")
case object MaskWritePort extends MemPort("mwrite") case object MaskedWritePort extends MemPort("mwrite")
case object ReadWritePort extends MemPort("rw") case object ReadWritePort extends MemPort("rw")
case object MaskReadWritePort extends MemPort("mrw") case object MaskedReadWritePort extends MemPort("mrw")
object MemPort { object MemPort {
val all = Set(ReadPort, WritePort, MaskWritePort, ReadWritePort, MaskReadWritePort) val all = Set(ReadPort, WritePort, MaskedWritePort, ReadWritePort, MaskedReadWritePort)
def apply(s: String): Option[MemPort] = MemPort.all.find(_.name == s) def apply(s: String): Option[MemPort] = MemPort.all.find(_.name == s)

4
macros/src/main/scala/Utils.scala
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@@ -107,7 +107,7 @@ object Utils {
writeEnable=Some(PolarizedPort(s"${portName}_en", ActiveHigh)), writeEnable=Some(PolarizedPort(s"${portName}_en", ActiveHigh)),
input=Some(PolarizedPort(s"${portName}_data", ActiveHigh)) input=Some(PolarizedPort(s"${portName}_data", ActiveHigh))
) } ) }
case MaskWritePort => { case MaskedWritePort => {
val portName = s"W${numW}" val portName = s"W${numW}"
numW += 1 numW += 1
MacroPort( MacroPort(
@@ -131,7 +131,7 @@ object Utils {
input=Some(PolarizedPort(s"${portName}_wdata", ActiveHigh)), input=Some(PolarizedPort(s"${portName}_wdata", ActiveHigh)),
output=Some(PolarizedPort(s"${portName}_rdata", ActiveHigh)) output=Some(PolarizedPort(s"${portName}_rdata", ActiveHigh))
) } ) }
case MaskReadWritePort => { case MaskedReadWritePort => {
val portName = s"RW${numRW}" val portName = s"RW${numRW}"
numRW += 1 numRW += 1
MacroPort( MacroPort(

4
tapeout/src/main/scala/transforms/RemoveUnusedModules.scala
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@@ -8,6 +8,8 @@ import firrtl.passes.Pass
import firrtl.annotations.{SingleTargetAnnotation, Annotation} import firrtl.annotations.{SingleTargetAnnotation, Annotation}
import firrtl.transforms.DontTouchAnnotation import firrtl.transforms.DontTouchAnnotation
// Removes all the unused modules in a circuit by recursing through every
// instance (starting at the main module)
class RemoveUnusedModules extends Transform { class RemoveUnusedModules extends Transform {
def inputForm = MidForm def inputForm = MidForm
def outputForm = MidForm def outputForm = MidForm
@@ -48,11 +50,13 @@ class RemoveUnusedModules extends Transform {
val renames = state.renames.getOrElse(RenameMap()) val renames = state.renames.getOrElse(RenameMap())
// This is what the annotation filter should look like, but for some reason it doesn't work.
//state.circuit.modules.filterNot { usedModuleSet contains _.name } foreach { x => renames.record(ModuleTarget(state.circuit.main, x.name), Seq()) } //state.circuit.modules.filterNot { usedModuleSet contains _.name } foreach { x => renames.record(ModuleTarget(state.circuit.main, x.name), Seq()) }
val newCircuit = Circuit(state.circuit.info, usedModuleSeq, state.circuit.main) val newCircuit = Circuit(state.circuit.info, usedModuleSeq, state.circuit.main)
val newAnnos = AnnotationSeq(state.annotations.toSeq.filter { _ match { val newAnnos = AnnotationSeq(state.annotations.toSeq.filter { _ match {
// XXX This is wrong, but it works for now // XXX This is wrong, but it works for now
// Tracked by https://github.com/ucb-bar/barstools/issues/36
case x: DontTouchAnnotation => false case x: DontTouchAnnotation => false
//case x: DontTouchAnnotation => usedModuleNames contains x.target.module //case x: DontTouchAnnotation => usedModuleNames contains x.target.module
case _ => true case _ => true