Style/Comments from review of #35

2019-02-13 10:02:34 -08:00
parent efd2f09b21
commit 1f58ea1e14
4 changed files with 12 additions and 9 deletions
--- a/macros/src/main/scala/Utils.scala
+++ b/macros/src/main/scala/Utils.scala
@@ -107,7 +107,7 @@ object Utils {
          writeEnable=Some(PolarizedPort(s"${portName}_en", ActiveHigh)),
          input=Some(PolarizedPort(s"${portName}_data", ActiveHigh))
        ) }
-      case MaskWritePort => {
+      case MaskedWritePort => {
        val portName = s"W${numW}"
        numW += 1
        MacroPort(
@@ -131,7 +131,7 @@ object Utils {
          input=Some(PolarizedPort(s"${portName}_wdata", ActiveHigh)),
          output=Some(PolarizedPort(s"${portName}_rdata", ActiveHigh))
        ) }
-      case MaskReadWritePort => {
+      case MaskedReadWritePort => {
        val portName = s"RW${numRW}"
        numRW += 1
        MacroPort(