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Style/Comments from review of #35

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This commit is contained in:
John Wright
2019-02-13 10:02:34 -08:00
committed by John Wright
parent efd2f09b21
commit 1f58ea1e14
4 changed files with 12 additions and 9 deletions
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7
macros/src/main/scala/MacroCompiler.scala
View File

@@ -755,10 +755,9 @@ object MacroCompiler extends App {
def run(args: List[String]) {
val (params, costParams, forcedMemories) = parseArgs(Map[MacroParam, String](), Map[String, String](), (Set.empty, Set.empty), args)
try {
val macros = if (params.get(MacrosFormat) == Some("conf")) {
Utils.filterForSRAM(Utils.readConfFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox)
} else {
Utils.filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox)
val macros = params.get(MacrosFormat) match {
case Some("conf") => Utils.filterForSRAM(Utils.readConfFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox)
case _ => Utils.filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(params.get(Macros))).get map (x => (new Macro(x)).blackbox)
}
if (macros.nonEmpty) {

6
macros/src/main/scala/MemConf.scala
View File

@@ -8,13 +8,13 @@ sealed abstract class MemPort(val name: String) { override def toString = name }
case object ReadPort extends MemPort("read")
case object WritePort extends MemPort("write")
case object MaskWritePort extends MemPort("mwrite")
case object MaskedWritePort extends MemPort("mwrite")
case object ReadWritePort extends MemPort("rw")
case object MaskReadWritePort extends MemPort("mrw")
case object MaskedReadWritePort extends MemPort("mrw")
object MemPort {
val all = Set(ReadPort, WritePort, MaskWritePort, ReadWritePort, MaskReadWritePort)
val all = Set(ReadPort, WritePort, MaskedWritePort, ReadWritePort, MaskedReadWritePort)
def apply(s: String): Option[MemPort] = MemPort.all.find(_.name == s)

4
macros/src/main/scala/Utils.scala
View File

@@ -107,7 +107,7 @@ object Utils {
writeEnable=Some(PolarizedPort(s"${portName}_en", ActiveHigh)),
input=Some(PolarizedPort(s"${portName}_data", ActiveHigh))
) }
case MaskWritePort => {
case MaskedWritePort => {
val portName = s"W${numW}"
numW += 1
MacroPort(
@@ -131,7 +131,7 @@ object Utils {
input=Some(PolarizedPort(s"${portName}_wdata", ActiveHigh)),
output=Some(PolarizedPort(s"${portName}_rdata", ActiveHigh))
) }
case MaskReadWritePort => {
case MaskedReadWritePort => {
val portName = s"RW${numRW}"
numRW += 1
MacroPort(