From 1e3d4aad460051c4fc030d10307097ea84766d33 Mon Sep 17 00:00:00 2001
From: Jerry Zhao <jerryz123@berkeley.edu>
Date: Mon, 10 Apr 2023 15:31:29 -0700
Subject: [PATCH] Update WithBackingScratchpad for firechip

---
 .../chipyard/src/main/scala/config/RocketConfigs.scala      | 4 ++--
 generators/firechip/src/main/scala/TargetConfigs.scala      | 6 +++---
 generators/testchipip                                       | 2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index a68ba55d..a0fab881 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -75,14 +75,14 @@ class L1ScratchpadRocketConfig extends Config(
 
 // DOC include start: mbusscratchpadrocket
 class MbusScratchpadOnlyRocketConfig extends Config(
-  new testchipip.WithMbusScratchpad(stripes=2, partitions=2) ++ // add 4 banks mbus backing scratchpad
+  new testchipip.WithMbusScratchpad(banks=2, partitions=2) ++               // add 2 partitions of 2 banks mbus backing scratchpad
   new freechips.rocketchip.subsystem.WithNoMemPort ++         // remove offchip mem port
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 // DOC include end: mbusscratchpadrocket
 
 class SbusScratchpadRocketConfig extends Config(
-  new testchipip.WithSbusScratchpad(base=0x70000000L, stripes=2, partitions=2) ++ // add 4 lanes sbus backing scratchpad
+  new testchipip.WithSbusScratchpad(base=0x70000000L, banks=4) ++ // add 4 banks sbus backing scratchpad
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)
 
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index c27abd50..1c821294 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -138,7 +138,7 @@ class WithFireSimConfigTweaks extends Config(
 class WithMinimalFireSimHighPerfConfigTweaks extends Config(
   new WithFireSimHighPerfClocking ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++
-  new testchipip.WithBackingScratchpad ++
+  new testchipip.WithMbusScratchpad ++
   new WithMinimalFireSimDesignTweaks
 )
 
@@ -148,7 +148,7 @@ class WithMinimalFireSimHighPerfConfigTweaks extends Config(
 class WithMinimalAndBlockDeviceFireSimHighPerfConfigTweaks extends Config(
   new WithFireSimHighPerfClocking ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++ // removes mem port for FASEDBridge to match against
-  new testchipip.WithBackingScratchpad ++ // adds backing scratchpad for memory to replace FASED model
+  new testchipip.WithMbusScratchpad ++ // adds backing scratchpad for memory to replace FASED model
   new testchipip.WithBlockDevice(true) ++ // add in block device
   new WithMinimalFireSimDesignTweaks
 )
@@ -329,7 +329,7 @@ class FireSim16LargeBoomConfig extends Config(
 class FireSimNoMemPortConfig extends Config(
   new WithDefaultFireSimBridges ++
   new freechips.rocketchip.subsystem.WithNoMemPort ++
-  new testchipip.WithBackingScratchpad ++
+  new testchipip.WithMbusScratchpad ++
   new WithFireSimConfigTweaks ++
   new chipyard.RocketConfig)
 
diff --git a/generators/testchipip b/generators/testchipip
index 8a1540ce..35d7e196 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 8a1540ce90405433ac377de5a6d331d34ff108df
+Subproject commit 35d7e1969d1d3e54d29a10901737d9b2ba2ab5a3