From 1e2667e0bce2ddd0f1e2faa63a085178f22aef52 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Thu, 16 Nov 2023 22:06:34 -0800 Subject: [PATCH] Add LLC bufExterior comment --- .../src/main/scala/config/fragments/SubsystemFragments.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala index f8119600..b57ea4cb 100644 --- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala @@ -18,11 +18,12 @@ class WithDTSTimebase(freqMHz: BigInt) extends Config((site, here, up) => { case DTSTimebase => freqMHz }) -// Adds buffers on the interior of the inclusive L2, to improve PD +// Adds buffers on the interior of the inclusive LLC, to improve PD class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => { case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerInterior=buffer, bufOuterInterior=buffer) }) +// Adds buffers on the exterior of the inclusive LLC, to improve PD class WithInclusiveCacheExteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => { case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerExterior=buffer, bufOuterExterior=buffer) })