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Fix fpga platforms cbus freq

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This commit is contained in:
Jerry Zhao
2023-10-21 15:48:01 -07:00
parent 2a6939cf0a
commit 1e26618e8d
5 changed files with 11 additions and 2 deletions
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2
fpga/src/main/scala/arty100t/Configs.scala
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@@ -32,6 +32,7 @@ class WithArty100TTweaks extends Config(
new chipyard.config.WithFrontBusFrequency(50.0) ++
new chipyard.config.WithSystemBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++
new chipyard.config.WithControlBusFrequency(50.0) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithNoDebug ++ // no jtag
@@ -62,5 +63,6 @@ class NoCoresArty100TConfig extends Config(
new WithArty100TTweaks ++
new chipyard.config.WithMemoryBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++ // Match the sbus and pbus frequency
new chipyard.config.WithControlBusFrequency(50.0) ++
new chipyard.config.WithBroadcastManager ++ // no l2
new chipyard.NoCoresConfig)