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bump rocket-chip and fix deprecated code in testchipip.GeneratorApp

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Howard Mao
2018-02-23 11:46:40 -08:00
parent eaff48e312
commit 1dfe9b1c9f
3 changed files with 3 additions and 3 deletions
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2
Makefrag
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@@ -38,7 +38,7 @@ CHISEL_ARGS ?=
$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir: $(rocketchip_stamp) $(extra_stamps) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) $(bootrom_img) $(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir: $(rocketchip_stamp) $(extra_stamps) $(call lookup_scala_srcs,$(base_dir)/src/main/scala) $(bootrom_img)
mkdir -p $(build_dir) mkdir -p $(build_dir)
cd $(base_dir) && $(SBT) "run-main $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)" cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"
$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v: $(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir $(FIRRTL_JAR) $(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v: $(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).fir $(FIRRTL_JAR)
$(FIRRTL) -i $< -o $@ -X verilog $(FIRRTL) -i $< -o $@ -X verilog

2
rocket-chip

Submodule rocket-chip updated: 8799508b1f...69b48b623a

2
testchipip

Submodule testchipip updated: f8d7bed3e5...3cd6ece873