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Fix unassigned clocks due to removing implicit clock from BaseSubsystem

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This commit is contained in:
Jerry Zhao
2023-10-18 18:59:22 -07:00
parent 686d9a5f44
commit 1d9dba517b
9 changed files with 15 additions and 11 deletions
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3
generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
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@@ -36,8 +36,7 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElement
// Set up clock domain // Set up clock domain
private val tlbus = locateTLBusWrapper(prciParams.slaveWhere) private val tlbus = locateTLBusWrapper(prciParams.slaveWhere)
val prci_ctrl_domain = LazyModule(new ClockSinkDomain(name=Some("chipyard-prci-control"))) val prci_ctrl_domain = tlbus.generateSynchronousDomain.suggestName("chipyard_prcictrl_domain")
prci_ctrl_domain.clockNode := tlbus.fixedClockNode
val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } } val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } }
prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar

1
generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -55,6 +55,7 @@ class AbstractConfig extends Config(
new chipyard.clocking.WithPassthroughClockGenerator ++ new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++ new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus
new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus
new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus
new testchipip.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address new testchipip.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address

7
generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
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@@ -199,12 +199,13 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: => Seq[T], p
trait CanHavePeripheryStreamingFIR extends BaseSubsystem { trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
val streamingFIR = p(GenericFIRKey) match { val streamingFIR = p(GenericFIRKey) match {
case Some(params) => { case Some(params) => {
val streamingFIR = LazyModule(new TLGenericFIRChain( val domain = pbus.generateSynchronousDomain.suggestName("fir_domain")
val streamingFIR = domain { LazyModule(new TLGenericFIRChain(
genIn = FixedPoint(8.W, 3.BP), genIn = FixedPoint(8.W, 3.BP),
genOut = FixedPoint(8.W, 3.BP), genOut = FixedPoint(8.W, 3.BP),
coeffs = Seq(1.U.asFixedPoint(0.BP), 2.U.asFixedPoint(0.BP), 3.U.asFixedPoint(0.BP)), coeffs = Seq(1.U.asFixedPoint(0.BP), 2.U.asFixedPoint(0.BP), 3.U.asFixedPoint(0.BP)),
params = params)) params = params)) }
pbus.coupleTo("streamingFIR") { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ } pbus.coupleTo("streamingFIR") { domain { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) } := _ }
Some(streamingFIR) Some(streamingFIR)
} }
case None => None case None => None

5
generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
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@@ -131,8 +131,9 @@ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughPara
trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem => trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
val passthrough = p(StreamingPassthroughKey) match { val passthrough = p(StreamingPassthroughKey) match {
case Some(params) => { case Some(params) => {
val streamingPassthroughChain = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) val domain = pbus.generateSynchronousDomain.suggestName("streaming_passthrough_domain")
pbus.coupleTo("streamingPassthrough") { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ } val streamingPassthroughChain = domain { LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) }
pbus.coupleTo("streamingPassthrough") { domain { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes)} := _ }
Some(streamingPassthroughChain) Some(streamingPassthroughChain)
} }
case None => None case None => None

2
generators/fft-generator

Submodule generators/fft-generator updated: 811951b44a...4e7e6cbbbc

2
generators/icenet

Submodule generators/icenet updated: 18e88b5779...d6a471f218

2
generators/rocket-chip

Submodule generators/rocket-chip updated: d48b45da56...8881ccd1ca

2
generators/testchipip

Submodule generators/testchipip updated: 24de6bca03...9785c2662d

2
generators/tracegen/src/main/scala/System.scala
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@@ -26,6 +26,8 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
lazy val clintOpt = None lazy val clintOpt = None
lazy val debugOpt = None lazy val debugOpt = None
lazy val plicOpt = None lazy val plicOpt = None
lazy val clintDomainOpt = None
lazy val plicDomainOpt = None
override lazy val module = new TraceGenSystemModuleImp(this) override lazy val module = new TraceGenSystemModuleImp(this)
} }