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Add Bringup on Arty100T config, using PMOD-gpio for ser-tl

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This commit is contained in:
Jerry Zhao
2023-11-08 20:00:03 -08:00
parent 8b6adb1525
commit 1d6ebb230b
3 changed files with 63 additions and 25 deletions
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50
fpga/src/main/scala/arty100t/HarnessBinders.scala
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@@ -1,6 +1,7 @@
package chipyard.fpga.arty100t
import chisel3._
import chisel3.experimental.{DataMirror, Direction}
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem.{PeripheryBusKey}
@@ -11,16 +12,17 @@ import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp, UARTParams}
import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
import sifive.blocks.devices.pinctrl.{BasePin}
import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
import sifive.fpgashells.shell._
import sifive.fpgashells.ip.xilinx._
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.clocks._
import chipyard._
import chipyard.harness._
import chipyard.iobinders._
import testchipip._
class WithArty100TUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({
class WithArty100TUARTTSI extends HarnessBinder({
case (th: HasHarnessInstantiators, port: UARTTSIPort) => {
val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
ath.io_uart_bb.bundle <> port.io.uart
@@ -41,3 +43,43 @@ class WithArty100TDDRTL extends HarnessBinder({
ddrClientBundle <> port.io
}
})
// Uses PMOD JA/JB
class WithArty100TSerialTLToGPIO extends HarnessBinder({
case (th: HasHarnessInstantiators, port: SerialTLPort) => {
val artyTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
val harnessIO = IO(port.io.cloneType).suggestName("serial_tl")
harnessIO <> port.io
val clkIO = IOPin(harnessIO.clock)
val packagePinsWithPackageIOs = Seq(
("G13", clkIO),
("B11", IOPin(harnessIO.bits.out.valid)),
("A11", IOPin(harnessIO.bits.out.ready)),
("D12", IOPin(harnessIO.bits.in.valid)),
("D13", IOPin(harnessIO.bits.in.ready)),
("B18", IOPin(harnessIO.bits.out.bits, 0)),
("A18", IOPin(harnessIO.bits.out.bits, 1)),
("K16", IOPin(harnessIO.bits.out.bits, 2)),
("E15", IOPin(harnessIO.bits.out.bits, 3)),
("E16", IOPin(harnessIO.bits.in.bits, 0)),
("D15", IOPin(harnessIO.bits.in.bits, 1)),
("C15", IOPin(harnessIO.bits.in.bits, 2)),
("J17", IOPin(harnessIO.bits.in.bits, 3))
)
packagePinsWithPackageIOs foreach { case (pin, io) => {
artyTh.xdc.addPackagePin(io, pin)
artyTh.xdc.addIOStandard(io, "LVCMOS33")
}}
// Don't add IOB to the clock, if its an input
if (DataMirror.directionOf(port.io.clock) == Direction.Input) {
packagePinsWithPackageIOs foreach { case (pin, io) => {
artyTh.xdc.addIOB(io)
}}
}
artyTh.sdc.addClock("ser_tl_clock", clkIO, 100)
artyTh.sdc.addGroup(pins = Seq(clkIO))
artyTh.xdc.clockDedicatedRouteFalse(clkIO)
}
})