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Remove GenerateSimFiles and use make instead

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This commit is contained in:
abejgonzalez
2021-05-06 00:27:11 -07:00
parent ff02977c5c
commit 1d52899736
10 changed files with 69 additions and 160 deletions
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16
sims/common-sim-flags.mk
View File

@@ -21,3 +21,19 @@ SIM_LDFLAGS = \
-lfesvr \
-ldramsim \
$(EXTRA_SIM_LDFLAGS)
SIM_FILE_REQS += \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \
$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v \
$(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \
$(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \
$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \
$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc

16
sims/vcs/Makefile
View File

@@ -31,6 +31,22 @@ include $(base_dir)/vcs.mk
default: $(sim)
debug: $(sim_debug)
#########################################################################################
# simulaton requirements
#########################################################################################
SIM_FILE_REQS += \
$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
# ignore *.h files since vcs has +incdir
$(sim_files): $(SIM_FILE_REQS)
mkdir -p $(dir $(sim_files))
cp -f $^ $(build_dir)
$(foreach file,\
$^,\
$(if $(filter %.h,$(file)),\
,\
echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
#########################################################################################
# import other necessary rules and variables
#########################################################################################

21
sims/verilator/Makefile
View File

@@ -30,6 +30,8 @@ sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
WAVEFORM_FLAG=-v$(sim_out_name).vcd
include $(base_dir)/sims/common-sim-flags.mk
# If verilator seed unspecified, verilator uses srand as random seed
ifdef RANDOM_SEED
SEED_FLAG=+verilator+seed+I$(RANDOM_SEED)
@@ -41,6 +43,23 @@ endif
default: $(sim)
debug: $(sim_debug)
#########################################################################################
# simulaton requirements
#########################################################################################
SIM_FILE_REQS += \
$(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \
$(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h
# add -FI for *.h files
$(sim_files): $(SIM_FILE_REQS)
mkdir -p $(dir $(sim_files))
cp -f $^ $(build_dir)
$(foreach file,\
$^,\
$(if $(filter %.h,$(file)),\
echo "-FI $(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;,\
echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
#########################################################################################
# import other necessary rules and variables
#########################################################################################
@@ -141,8 +160,6 @@ VERILATOR_NONCC_OPTS = \
#----------------------------------------------------------------------------------------
# gcc configuration/optimization
#----------------------------------------------------------------------------------------
include $(base_dir)/sims/common-sim-flags.mk
VERILATOR_CXXFLAGS = \
$(SIM_CXXFLAGS) \
$(RUNTIME_PROFILING_CFLAGS) \