Reverse documentation on breaking prereqs

This commit is contained in:
abejgonzalez
2021-10-25 22:29:38 -07:00
parent b7fd1ffae2
commit 1d3d8e4e01
3 changed files with 16 additions and 6 deletions

View File

@@ -137,7 +137,6 @@ Now with all of that done, we can go ahead and run our simulation.
.. code-block:: shell
cd sims/verilator
make CONFIG=GCDTLRocketConfig
make CONFIG=GCDTLRocketConfig BINARY=../../tests/gcd.riscv run-binary