Merge branch 'add-disallowPackedArrays' of https://github.com/ucb-bar/chipyard into add-disallowPackedArrays

build.sbt

@@ -12,7 +12,10 @@ lazy val commonSettings = Seq(
   assembly / assemblyMergeStrategy := { _ match {
     case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
     case _ => MergeStrategy.first}},
-  scalacOptions ++= Seq("-deprecation","-unchecked"),
+  scalacOptions ++= Seq(
+    "-deprecation",
+    "-unchecked",
+    "-Ymacro-annotations"), // fix hierarchy API
   unmanagedBase := (chipyardRoot / unmanagedBase).value,
   allDependencies := {
     // drop specific maven dependencies in subprojects in favor of Chipyard's version
@@ -170,7 +173,7 @@ lazy val tracegen = (project in file("generators/tracegen"))
   .settings(commonSettings)
 
 lazy val icenet = (project in file("generators/icenet"))
-  .dependsOn(testchipip, rocketchip)
+  .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
 
@@ -206,7 +209,7 @@ lazy val sha3 = (project in file("generators/sha3"))
   .settings(commonSettings)
 
 lazy val gemmini = (project in file("generators/gemmini"))
-  .dependsOn(testchipip, rocketchip)
+  .dependsOn(rocketchip)
   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(chiselTestSettings)
   .settings(commonSettings)

common.mk

@@ -18,6 +18,7 @@ HELP_COMPILATION_VARIABLES += \
 "   EXTRA_SIM_REQS            = additional make requirements to build the simulator" \
 "   ENABLE_SBT_THIN_CLIENT    = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \
 "   ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \
+" 	ENABLE_VLSI_FLOW          = if set, add compilation flags to enable the vlsi flow for hammer \
 "   EXTRA_CHISEL_OPTIONS      = additional options to pass to the Chisel compiler" \
 "   EXTRA_FIRRTL_OPTIONS      = additional options to pass to the FIRRTL compiler"
 
@@ -26,6 +27,11 @@ EXTRA_SIM_CXXFLAGS   ?=
 EXTRA_SIM_LDFLAGS    ?=
 EXTRA_SIM_SOURCES    ?=
 EXTRA_SIM_REQS       ?=
+ENABLE_CUSTOM_FIRRTL_PASS += $(ENABLE_VLSI_FLOW)
+
+
+$(info $$ENABLE_CUSTOM_FIRRTL_PASS is [${ENABLE_CUSTOM_FIRRTL_PASS}])
+$(info $$ENABLE_VLSI_FLOW is [${ENABLE_VLSI_FLOW}])
 
 #----------------------------------------------------------------------------
 HELP_SIMULATION_VARIABLES += \
@@ -126,10 +132,20 @@ define mfc_extra_anno_contents
 	}
 ]
 endef
+define sfc_extra_low_transforms_anno_contents
+[
+	{
+		"class": "firrtl.stage.RunFirrtlTransformAnnotation",
+		"transform": "barstools.tapeout.transforms.ExtraLowTransforms"
+	}
+]
+endef
 export mfc_extra_anno_contents
-$(FINAL_ANNO_FILE) $(MFC_EXTRA_ANNO_FILE): $(ANNO_FILE)
+export sfc_extra_low_transforms_anno_contents
+$(EXTRA_ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) &: $(ANNO_FILE)
 	echo "$$mfc_extra_anno_contents" > $(MFC_EXTRA_ANNO_FILE)
-	jq -s '[.[][]]' $(ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE)
+	echo "$$sfc_extra_low_transforms_anno_contents" > $(SFC_EXTRA_ANNO_FILE)
+	jq -s '[.[][]]' $(ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) > $(EXTRA_ANNO_FILE)
 
 .PHONY: firrtl
 firrtl: $(FIRRTL_FILE) $(FINAL_ANNO_FILE)
@@ -149,7 +165,6 @@ SFC_MFC_TARGETS = \
 
 SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
 
-
 # DOC include start: FirrtlCompiler
 # There are two possible cases for this step. In the first case, SFC
 # compiles Chisel to CHIRRTL, and MFC compiles CHIRRTL to Verilog. Otherwise,
@@ -161,8 +176,7 @@ SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
 # hack: lower to low firrtl if Fixed types are found
 # hack: when using dontTouch, io.cpu annotations are not removed by SFC,
 # hence we remove them manually by using jq before passing them to firtool
-$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES)
+$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(FINAL_ANNO_FILE) &: $(FIRRTL_FILE) $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE)
-	rm -rf $(GEN_COLLATERAL_DIR)
 ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS))
 	$(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none))
 	$(eval EXTRA_FIRRTL_OPTIONS += $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), $(SFC_REPL_SEQ_MEM),))
@@ -170,6 +184,11 @@ else
 	$(eval SFC_LEVEL := low)
 	$(eval EXTRA_FIRRTL_OPTIONS += $(SFC_REPL_SEQ_MEM))
 endif
+	if [ $(SFC_LEVEL) = low ]; then jq -s '[.[][]]' $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi
+	if [ $(SFC_LEVEL) = none ]; then cat $(EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi
+
+$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS)
+	rm -rf $(GEN_COLLATERAL_DIR)
 	$(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateModelStageMain,\
 		--no-dedup \
 		--output-file $(SFC_FIRRTL_BASENAME) \
@@ -179,13 +198,12 @@ endif
 		--annotation-file $(FINAL_ANNO_FILE) \
 		--log-level $(FIRRTL_LOGLEVEL) \
 		--allow-unrecognized-annotations \
-		-DX $(SFC_LEVEL) \
 		-X $(SFC_LEVEL) \
-		$(EXTRA_FIRRTL_OPTIONS)) # -X and -DX are duplicates to allow for extra FIRRTL passes to be run
+		$(EXTRA_FIRRTL_OPTIONS))
 	-mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) # Optionally change file type when SFC generates LowFIRRTL
-	@if [ "$(SFC_LEVEL)" = low ]; then cat $(SFC_ANNO_FILE) | jq 'del(.[] | select(.target | test("io.cpu"))?)' > /tmp/unnec-anno-deleted.sfc.anno.json; fi
+	@if [ $(SFC_LEVEL) = low ]; then cat $(SFC_ANNO_FILE) | jq 'del(.[] | select(.target | test("io.cpu"))?)' > /tmp/unnec-anno-deleted.sfc.anno.json; fi
-	@if [ "$(SFC_LEVEL)" = low ]; then cat /tmp/unnec-anno-deleted.sfc.anno.json | jq 'del(.[] | select(.class | test("SRAMAnnotation"))?)' > /tmp/unnec-anno-deleted2.sfc.anno.json; fi
+	@if [ $(SFC_LEVEL) = low ]; then cat /tmp/unnec-anno-deleted.sfc.anno.json | jq 'del(.[] | select(.class | test("SRAMAnnotation"))?)' > /tmp/unnec-anno-deleted2.sfc.anno.json; fi
-	@if [ "$(SFC_LEVEL)" = low ]; then cat /tmp/unnec-anno-deleted2.sfc.anno.json > $(SFC_ANNO_FILE) && rm /tmp/unnec-anno-deleted.sfc.anno.json && rm /tmp/unnec-anno-deleted2.sfc.anno.json; fi
+	@if [ $(SFC_LEVEL) = low ]; then cat /tmp/unnec-anno-deleted2.sfc.anno.json > $(SFC_ANNO_FILE) && rm /tmp/unnec-anno-deleted.sfc.anno.json && rm /tmp/unnec-anno-deleted2.sfc.anno.json; fi
 	firtool \
 		--format=fir \
 		--dedup \

docs/Customization/DMA-Devices.rst

@@ -20,7 +20,7 @@ that writes zeros to the memory at a configured address.
     :start-after: DOC include start: DigitalTop
     :end-before: DOC include end: DigitalTop
 
-We use ``TLHelper.makeClientNode`` to create a TileLink client node for us.
+We use ``TLClientNode`` to create a TileLink client node for us.
 We then connect the client node to the memory system through the front bus (fbus).
 For more info on creating TileLink client nodes, take a look at :ref:`TileLink-Diplomacy-Reference/NodeTypes:Client Node`.
 

docs/TileLink-Diplomacy-Reference/NodeTypes.rst

@@ -16,8 +16,7 @@ on the C channel, and send grant acknowledgements on the E channel.
 
 The L1 caches and DMA devices in RocketChip/Chipyard have client nodes.
 
-You can add a TileLink client node to your LazyModule using the TLHelper
+You can add a TileLink client node to your LazyModule like so:
-object from testchipip like so:
 
 .. literalinclude:: ../../generators/chipyard/src/main/scala/example/NodeTypes.scala
     :language: scala
@@ -48,8 +47,7 @@ generators optimize the hardware by not arbitrating the client to managers with
 address ranges that don't overlap with its visibility.
 
 Inside your lazy module implementation, you can call ``node.out`` to get a
-list of bundle/edge pairs. If you used the TLHelper, you only specified a
+list of bundle/edge pairs.
-single client edge, so this list will only have one pair.
 
 The ``tl`` bundle is a Chisel hardware bundle that connects to the IO of this
 module. It contains two (in the case of TL-UL and TL-UH) or five (in the case
@@ -65,8 +63,7 @@ Manager Node
 ------------
 
 TileLink managers take requests from clients on the A channel and send
-responses back on the D channel. You can create a manager node using the
+responses back on the D channel. You can create a manager like so:
-TLHelper like so:
 
 .. literalinclude:: ../../generators/chipyard/src/main/scala/example/NodeTypes.scala
     :language: scala

docs/VLSI/Advanced-Usage.rst

@@ -3,14 +3,22 @@
 Advanced Usage
 ==============
 
-Hammer Development
+Hammer Development and Upgrades
-------------------
+-------------------------------
 If you need to develop Hammer within Chipyard or use a version of Hammer beyond the latest PyPI release, clone the `Hammer repository <https://github.com/ucb-bar/hammer>`__ somewhere else on your disk. Then:
 
 .. code-block:: shell
     
     pip install -e <path/to/hammer>
 
+To bump specific plugins to their latest commits and install them, you can use the upgrade script from the Chipyard root directory, with arguments for match patterns for the plugin names:
+
+.. code-block:: shell
+
+    ./scripts/upgrade-vlsi.sh <pattern(s)>
+
+If you would like to upgrade your Hammer installation to the latest PyPI release and bump all of your plugins at once, run the above script without arguments. WARNING: this may pull in plugin changes that are newer than the latest Hammer release and cause incompatibility issues.
+
 Alternative RTL Flows
 ---------------------
 The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom Verilog module through, one only needs to append the following environment variables to the ``make buildfile`` command (or edit them directly in the Makefile).
@@ -95,6 +103,6 @@ With the Synopsys plugin, hierarchical RTL and gate-level simulation is supporte
 
 * ``redo-`` can be appended to all above targets to break dependency tracking, like described above.
 
-* ``-$(VLSI_TOP)`` suffixes denote simulations/power analysis on a submodule in a hierarchical flow. Note that you must provide the testbenches for these modules since the default testbench only simulates a Chipyard-based ``ChipTop`` DUT instance.
+* ``-$(VLSI_TOP)`` suffixes denote simulations/power analysis on a submodule in a hierarchical flow (remember to override this variable). Note that you must provide the testbenches for these modules since the default testbench only simulates a Chipyard-based ``ChipTop`` DUT instance.
 
 The simulation configuration (e.g. binaries) can be edited for your design. See the ``Makefile`` and refer to Hammer's documentation for how to set up simulation parameters for your design.

docs/VLSI/Basic-Flow.rst

@@ -295,8 +295,11 @@ For example, if we choose to specifiy the previously mentioned ``GemminiRocketCo
             bottom: 0
 
 
-In this specification, ``vlsi.inputs.hierarchical.mode`` indicates the manual specification of the heirarchy tree (which is the only mode currently supported by Hammer), ``vlsi.inputs.hiearchical.top_module`` sets the root of the hierarchical tree, ``vlsi.inputs.hierarchical.manual_modules`` enumerates the tree of hierarchical modules, and ``vlsi.inputs.hierarchical.manual_placement_constraints`` enumerates the floorplan for each module.
+In this specification, ``vlsi.inputs.hierarchical.mode`` indicates the manual specification of the hierarchy tree (which is the only mode currently supported by Hammer), ``vlsi.inputs.hierarchical.top_module`` sets the root of the hierarchical tree, ``vlsi.inputs.hierarchical.manual_modules`` enumerates the tree of hierarchical modules, and ``vlsi.inputs.hierarchical.manual_placement_constraints`` enumerates the floorplan for each module.
 
+For more information about the Hammer hierarchical flow and specifying the hierarchy and constraints, visit the `Hammer documentation <https://hammer-vlsi.readthedocs.io/en/stable/Hammer-Use/Hierarchical.html>`__.
+
+.. Note:: You must generate the hierarchical hierarchy BEFORE running the ``make buildfile`` target. This is because Hammer encodes its hierarchical flow graph in a generated Makefile in ``$(OBJ_DIR)/hammer.d``. If you modify your physical hierarchy, you must wipe and regenerate this Makefile. Finally, you must always override the ``VLSI_TOP`` variable to be the hierarchical block that you are working on. This is required for hierarchical simulation and power flows.
 
 .. Specifying a Custom Floorplan
 .. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

generators/chipyard/src/main/scala/example/InitZero.scala

@@ -5,14 +5,14 @@ import chisel3.util._
 import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
 import freechips.rocketchip.config.{Parameters, Field, Config}
 import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}
-import testchipip.TLHelper
+import freechips.rocketchip.tilelink._
 
 case class InitZeroConfig(base: BigInt, size: BigInt)
 case object InitZeroKey extends Field[Option[InitZeroConfig]](None)
 
 class InitZero(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeClientNode(
+  val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
-    name = "init-zero", sourceId = IdRange(0, 1))
+    name = "init-zero", sourceId = IdRange(0, 1))))))
 
   lazy val module = new InitZeroModuleImp(this)
 }

generators/chipyard/src/main/scala/example/NodeTypes.scala

@@ -3,7 +3,6 @@ package chipyard.example
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
-import testchipip.TLHelper
 
 // These modules are not meant to be synthesized.
 // They are used as examples in the documentation and are only here
@@ -11,11 +10,11 @@ import testchipip.TLHelper
 
 // DOC include start: MyClient
 class MyClient(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeClientNode(TLMasterParameters.v1(
+  val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
     name = "my-client",
     sourceId = IdRange(0, 4),
     requestFifo = true,
-    visibility = Seq(AddressSet(0x10000, 0xffff))))
+    visibility = Seq(AddressSet(0x10000, 0xffff)))))))
 
   lazy val module = new LazyModuleImp(this) {
     val (tl, edge) = node.out(0)
@@ -29,7 +28,7 @@ class MyClient(implicit p: Parameters) extends LazyModule {
 class MyManager(implicit p: Parameters) extends LazyModule {
   val device = new SimpleDevice("my-device", Seq("tutorial,my-device0"))
   val beatBytes = 8
-  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
+  val node = TLManagerNode(Seq(TLSlavePortParameters.v1(Seq(TLManagerParameters(
     address = Seq(AddressSet(0x20000, 0xfff)),
     resources = device.reg,
     regionType = RegionType.UNCACHED,
@@ -40,7 +39,7 @@ class MyManager(implicit p: Parameters) extends LazyModule {
     supportsPutFull = TransferSizes(1, beatBytes),
     supportsPutPartial = TransferSizes(1, beatBytes),
     supportsHint = TransferSizes(1, beatBytes),
-    fifoId = Some(0)))
+    fifoId = Some(0))), beatBytes)))
 
   lazy val module = new LazyModuleImp(this) {
     val (tl, edge) = node.in(0)
@@ -50,7 +49,8 @@ class MyManager(implicit p: Parameters) extends LazyModule {
 
 // DOC include start: MyClient1+MyClient2
 class MyClient1(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeClientNode("my-client1", IdRange(0, 1))
+  val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
+    "my-client1", IdRange(0, 1))))))
 
   lazy val module = new LazyModuleImp(this) {
     // ...
@@ -58,7 +58,8 @@ class MyClient1(implicit p: Parameters) extends LazyModule {
 }
 
 class MyClient2(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeClientNode("my-client2", IdRange(0, 1))
+  val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
+    "my-client2", IdRange(0, 1))))))
 
   lazy val module = new LazyModuleImp(this) {
     // ...
@@ -83,8 +84,8 @@ class MyClientGroup(implicit p: Parameters) extends LazyModule {
 
 // DOC include start: MyManagerGroup
 class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
+  val node = TLManagerNode(Seq(TLSlavePortParameters.v1(Seq(TLManagerParameters(
-    address = Seq(AddressSet(0x0, 0xfff))))
+    address = Seq(AddressSet(0x0, 0xfff)))), beatBytes)))
 
   lazy val module = new LazyModuleImp(this) {
     // ...
@@ -92,8 +93,8 @@ class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
 }
 
 class MyManager2(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
+  val node = TLManagerNode(Seq(TLSlavePortParameters.v1(Seq(TLManagerParameters(
-    address = Seq(AddressSet(0x1000, 0xfff))))
+    address = Seq(AddressSet(0x1000, 0xfff)))), beatBytes)))
 
   lazy val module = new LazyModuleImp(this) {
     // ...

generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala

@@ -13,7 +13,7 @@ private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptio
       longOption = "legacy-configs",
       toAnnotationSeq = a => {
         val split = a.split(':')
-        assert(split.length == 2)
+        assert(split.length == 2, s"'${a}' split by ':' doesn't yield two things")
         val packageName = split.head
         val configs     = split.last.split("_")
         Seq(new ConfigsAnnotation(configs map { config => if (config contains ".") s"${config}" else s"${packageName}.${config}" } ))

scripts/build-setup.sh

@@ -91,7 +91,7 @@ run_step() {
 # Check for this, since many users will be attempting to use this with gemmini
 if [ $TOOLCHAIN_TYPE == "esp-tools" ]; then
     while true; do
-        read -p "WARNING: You are trying to install the esp-tools toolchain."$'n'"This should ONLY be used for Hwacha development."$'\n'"Gemmini should be used with riscv-tools."$'\n'"Type \"y\" to continue if this is intended, or \"n\" if not: " validate
+        read -p "WARNING: You are trying to install the esp-tools toolchain."$'\n'"This should ONLY be used for Hwacha development."$'\n'"Gemmini should be used with riscv-tools."$'\n'"Type \"y\" to continue if this is intended, or \"n\" if not: " validate
         case "$validate" in
             y | Y)
                 echo "Installing esp-tools."

scripts/tutorial-patches/build.sbt.patch

@@ -27,4 +27,4 @@ index ec36a85f..c0c2849a 100644
 +//  .settings(commonSettings)
 
  lazy val gemmini = (project in file("generators/gemmini"))
-   .dependsOn(testchipip, rocketchip)
+   .dependsOn(rocketchip)

scripts/upgrade-vlsi.sh

@@ -1,8 +1,14 @@
 #!/usr/bin/env bash
 
+# This script updates Hammer and plugins.
+# ./scripts/upgrade-vlsi.sh <pattern(s)> will upgrade plugins matching the pattern list.
+# ./scripts/upgrade-vlsi.sh will upgrade all plugins and bump hammer-vlsi to the latest released version. Only do this upon a new Hammer release.
+
 # exit script if any command fails
 set -e
 set -o pipefail
+# except for grep in the pipe
+clgrep() { grep $@ || test $? = 1; }
 
 # exit script if not in Chipyard conda env
 if [[ `basename $CONDA_PREFIX` != .conda-env ]]; then
@@ -11,24 +17,31 @@ if [[ `basename $CONDA_PREFIX` != .conda-env ]]; then
 fi
 
 # Get hammer submodules
-package_names=$(git ls-files --stage | grep 160000 | awk '$4 ~/vlsi\/hammer.*/ {print $4}')
+if [ $# -gt 0 ]; then
-package_list=(${package_names})
+    patterns=()
-plen="${#package_list[@]}"
+    for arg in $@; do
-
+        patterns+=("-e" $arg)
-if [[ ${plen} -gt 0 ]]; then
-    for p in "${package_list[@]}"; do
-        cd ${p}
-        echo "Updating current directory: $PWD"
-        git checkout `basename "$(git rev-parse --abbrev-ref origin/HEAD)"`
-        git pull
-        cd - > /dev/null
-        git add ${p}
-        pip install -e ${p} --upgrade
     done
+    package_list=($(git ls-files --stage | grep 160000 | clgrep ${patterns[@]} | awk '$4 ~/vlsi\/hammer.*/ {print $4}'))
+else
+    package_list=($(git ls-files --stage | grep 160000 | awk '$4 ~/vlsi\/hammer.*/ {print $4}'))
+    # Also upgrade hammer-vlsi.
+    pip install hammer-vlsi --upgrade
 fi
 
-# Upgrade hammer-vlsi separately.
+# exit if requested package not found (case of an unmatched pattern in a list is not handled)
-pip install hammer-vlsi --upgrade
+if [ -z ${package_list} ]; then
-
+    echo "No Hammer plugins matching these patterns found: $@"
-
+    exit
+fi
 
+# upgrade to latest commit in default branch
+for p in ${package_list[@]}; do
+    echo "Updating ${p}"
+    cd ${p}
+    git checkout `basename "$(git rev-parse --abbrev-ref origin/HEAD)"`
+    git pull
+    cd - > /dev/null
+    git add ${p}
+    pip install -e ${p} --upgrade
+done

variables.mk

@@ -146,6 +146,7 @@ endif
 # chisel generated outputs
 FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
 ANNO_FILE   ?= $(build_dir)/$(long_name).anno.json
+EXTRA_ANNO_FILE ?= $(build_dir)/$(long_name).extra.anno.json
 
 # chisel anno modification output
 MFC_EXTRA_ANNO_FILE ?= $(build_dir)/$(long_name).extrafirtool.anno.json
@@ -154,6 +155,7 @@ FINAL_ANNO_FILE ?= $(build_dir)/$(long_name).appended.anno.json
 # scala firrtl compiler (sfc) outputs
 SFC_FIRRTL_BASENAME ?= $(build_dir)/$(long_name).sfc
 SFC_FIRRTL_FILE ?= $(SFC_FIRRTL_BASENAME).fir
+SFC_EXTRA_ANNO_FILE ?= $(build_dir)/$(long_name).extrasfc.anno.json
 SFC_ANNO_FILE ?= $(build_dir)/$(long_name).sfc.anno.json
 
 # firtool compiler outputs

vlsi/power.mk

@@ -2,8 +2,9 @@ POWER_CONF = $(OBJ_DIR)/power-inputs.yml
 POWER_RTL_CONF = $(OBJ_DIR)/power-rtl-inputs.yml
 POWER_SYN_CONF = $(OBJ_DIR)/power-syn-inputs.yml
 POWER_PAR_CONF = $(OBJ_DIR)/power-par-inputs.yml
+POWER_PAR_HIER_CONF = $(OBJ_DIR)/power-par-$(VLSI_TOP)-inputs.yml
 
-.PHONY: $(POWER_CONF) $(POWER_RTL_CONF) $(POWER_SYN_CONF) $(POWER_PAR_CONF)
+.PHONY: $(POWER_CONF) $(POWER_RTL_CONF) $(POWER_SYN_CONF) $(POWER_PAR_CONF) $(POWER_PAR_HIER_CONF)
 
 $(POWER_CONF): $(VLSI_RTL)
 	mkdir -p $(dir $@)
@@ -45,6 +46,12 @@ $(POWER_PAR_CONF): $(VLSI_RTL)
 	echo "  level: par" >> $@
 	echo "  database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@
 
+$(POWER_PAR_HIER_CONF): $(VLSI_RTL)
+	echo "vlsi.core.power_tool: hammer.power.voltus" > $@
+	echo "power.inputs:" >> $@
+	echo "  level: par" >> $@
+	echo "  database: '$(OBJ_DIR)/par-$(VLSI_TOP)/$(VLSI_TOP)_FINAL'" >> $@
+
 power-rtl: $(POWER_CONF) $(POWER_RTL_CONF) sim-rtl-debug
 power-rtl-$(VLSI_TOP): $(POWER_CONF) $(POWER_RTL_CONF) sim-rtl-debug-$(VLSI_TOP)
 power-rtl: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_RTL_CONF)
@@ -64,12 +71,12 @@ redo-power-syn: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_SYN_CO
 redo-power-syn-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_SYN_CONF)
 
 power-par: $(POWER_CONF) $(POWER_PAR_CONF) sim-par-debug
-power-par-$(VLSI_TOP): $(POWER_CONF) $(POWER_PAR_CONF) sim-par-debug-$(VLSI_TOP)
+power-par-$(VLSI_TOP): $(POWER_CONF) $(POWER_PAR_HIER_CONF) sim-par-debug-$(VLSI_TOP)
 power-par: override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_CONF)
-power-par-$(VLSI_TOP): override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_CONF)
+power-par-$(VLSI_TOP): override HAMMER_POWER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_HIER_CONF)
 redo-power-par: $(POWER_CONF) $(POWER_PAR_CONF)
-redo-power-par-$(VLSI_TOP): $(POWER_CONF) $(POWER_PAR_CONF)
+redo-power-par-$(VLSI_TOP): $(POWER_CONF) $(POWER_PAR_HIER_CONF)
 redo-power-par: override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_CONF)
-redo-power-par-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_CONF)
+redo-power-par-$(VLSI_TOP): override HAMMER_EXTRA_ARGS += -p $(POWER_CONF) -p $(POWER_PAR_HIER_CONF)
 
 $(OBJ_DIR)/power-%/power-output-full.json: private override HAMMER_EXTRA_ARGS += $(HAMMER_POWER_EXTRA_ARGS)