From 1c76515f17324ca631d620360f36049465c2ff14 Mon Sep 17 00:00:00 2001
From: Richard Yan <yrh@berkeley.edu>
Date: Fri, 15 Sep 2023 11:18:22 -0700
Subject: [PATCH] add args.bin and large extmem to config

---
 .../chipyard/src/main/scala/System.scala      |  8 ++++---
 .../src/main/scala/config/RocketConfigs.scala | 21 +++++++++++++------
 generators/rocket-chip                        |  2 +-
 3 files changed, 21 insertions(+), 10 deletions(-)

diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala
index 5643e380..421e8bbf 100644
--- a/generators/chipyard/src/main/scala/System.scala
+++ b/generators/chipyard/src/main/scala/System.scala
@@ -6,13 +6,14 @@
 package chipyard
 
 import chisel3._
-
-import org.chipsalliance.cde.config.{Parameters, Field}
+import org.chipsalliance.cde.config.{Field, Parameters}
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.util.{DontTouch}
+import freechips.rocketchip.util.DontTouch
+
+import java.nio.file.Paths
 
 // ---------------------------------------------------------------------
 // Base system that uses the debug test module (dtm) to bringup the core
@@ -31,6 +32,7 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
 
   val bootROM  = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) }
   val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }
+  p(RadianceArgsROMLocated()).foreach { BootROM.attachArgs(_, this, CBUS) }
 
   // If there is no bootrom, the tile reset vector bundle will be tied to zero
   if (bootROM.isEmpty) {
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index 27c93394..5024d0bd 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -1,8 +1,9 @@
 package chipyard
 
-import org.chipsalliance.cde.config.{Config}
-import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
-
+import org.chipsalliance.cde.config.{Config, Field}
+import freechips.rocketchip.diplomacy.AsynchronousCrossing
+import freechips.rocketchip.devices.tilelink.{RadianceArgsROMLocated, RadianceArgsROMParams}
+import freechips.rocketchip.subsystem.WithExtMemSize
 // --------------
 // Rocket Configs
 // --------------
@@ -11,12 +12,20 @@ class RocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
   new chipyard.config.AbstractConfig)
 
+
+class WithRadArgsROM(filename: String) extends Config((site, here, up) => {
+  case RadianceArgsROMLocated() => up(RadianceArgsROMLocated()).map(_.copy(
+    contentFileName = filename))
+})
+
 class RadianceConfig extends Config(
   new freechips.rocketchip.subsystem.WithRadianceCores() ++
-  new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
-  new freechips.rocketchip.subsystem.WithNoMemPort ++
-  new testchipip.WithSbusScratchpad(banks=2) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  // new freechips.rocketchip.subsystem.WithNoMemPort ++
+  // new testchipip.WithSbusScratchpad(banks=2) ++
   // new testchipip.WithMbusScratchpad(banks=2) ++
+  new WithExtMemSize(BigInt("80000000", 16)) ++
+  new WithRadArgsROM("sims/vcs/args.bin") ++
   new chipyard.config.AbstractConfig)
 
 class TinyRocketConfig extends Config(
diff --git a/generators/rocket-chip b/generators/rocket-chip
index fdbcb6c6..07fd4c88 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit fdbcb6c64b2648959a3af1df7c1b6cea00f41477
+Subproject commit 07fd4c88aeee0aa57c73a264fa08efb51c420dce