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update docs for release

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joey0320
2023-03-11 16:52:35 -08:00
parent a8c9c8271e
commit 1c1b0effa3
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docs/Tools/FIRRTL.rst
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@@ -3,7 +3,7 @@ FIRRTL
`FIRRTL <https://github.com/freechipsproject/firrtl>`__ is an intermediate representation of your circuit.
It is emitted by the Chisel compiler and is used to translate Chisel source files into another representation such as Verilog.
Without going into too much detail, FIRRTL is consumed by a FIRRTL compiler (another Scala program) which passes the circuit through a series of circuit-level transformations.
Without going into too much detail, FIRRTL is consumed by FIRRTL compilers which passes the circuit through a series of circuit-level transformations.
An example of a FIRRTL pass (transformation) is one that optimizes out unused signals.
Once the transformations are done, a Verilog file is emitted and the build process is done.