wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Rename VortexFatBank in configs

Browse Source
This commit is contained in:
Hansung Kim
2023-11-22 16:27:36 -08:00
parent c1d5b06348
commit 1c1143bb6c
1 changed files with 1 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
generators/chipyard/src/main/scala/config/RocketConfigs.scala
View File

@@ -52,7 +52,7 @@ class RadianceFatBankROMConfig extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++ new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++ new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++ new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++
new freechips.rocketchip.subsystem.WithVortexFatBank(nBanks = 4)++ new freechips.rocketchip.subsystem.WithVortexL1Banks(nBanks = 1)++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
new WithExtMemSize(BigInt("80000000", 16)) ++ new WithExtMemSize(BigInt("80000000", 16)) ++
@@ -62,7 +62,6 @@ class RadianceFatBankROMConfig extends Config(
new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++ new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++
new AbstractConfig) new AbstractConfig)
class RadianceConfig extends Config( class RadianceConfig extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++ new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++