From 1b7457d2fc894e8a57b1710cb3362e4923a447cd Mon Sep 17 00:00:00 2001 From: "-T.K.-" Date: Wed, 7 Dec 2022 19:34:35 -0800 Subject: [PATCH] FIX: fix Arty FPGA reset signal (#1257) --- fpga/src/main/scala/arty/TestHarness.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/src/main/scala/arty/TestHarness.scala b/fpga/src/main/scala/arty/TestHarness.scala index fdb91a47..af9462d1 100644 --- a/fpga/src/main/scala/arty/TestHarness.scala +++ b/fpga/src/main/scala/arty/TestHarness.scala @@ -17,7 +17,7 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell // Convert harness resets from Bool to Reset type. val hReset = Wire(Reset()) - hReset := ck_rst + hReset := ~ck_rst val dReset = Wire(AsyncReset()) dReset := reset_core.asAsyncReset