Make the directory structure match the packages

All tests run as they did prior to the changes

macros/src/main/scala/barstools/macros/CostMetric.scala

@@ -67,8 +67,9 @@ object OldMetric extends CostMetric with CostMetricCompanion {
  */
 class ExternalMetric(path: String) extends CostMetric {
   import mdf.macrolib.Utils.writeMacroToPath
+
   import java.io._
-  import scala.language.postfixOps // for !! postfix op
+  import scala.language.postfixOps
   import sys.process._
 
   override def cost(mem: Macro, lib: Macro): Option[Double] = {

macros/src/main/scala/barstools/macros/MacroCompiler.scala

@@ -8,18 +8,17 @@
 
 package barstools.macros
 
-import firrtl._
-import firrtl.ir._
-import firrtl.PrimOps
+import barstools.macros.Utils._
+import firrtl.CompilerUtils.getLoweringTransforms
 import firrtl.Utils._
 import firrtl.annotations._
-import firrtl.transforms.{NoDCEAnnotation}
-import firrtl.CompilerUtils.getLoweringTransforms
-import mdf.macrolib.{PolarizedPort, PortPolarity, SRAMMacro, SRAMGroup, SRAMCompiler}
-import scala.collection.mutable.{ArrayBuffer, HashMap}
+import firrtl.ir._
+import firrtl.{PrimOps, _}
+import mdf.macrolib._
+
 import java.io.{File, FileWriter}
-import scala.io.{Source}
-import Utils._
+import scala.collection.mutable.{ArrayBuffer, HashMap}
+import scala.io.Source
 
 case class MacroCompilerException(msg: String) extends Exception(msg)
 

macros/src/main/scala/barstools/macros/SynFlops.scala

@@ -2,11 +2,11 @@
 
 package barstools.macros
 
+import barstools.macros.Utils._
+import firrtl.Utils._
 import firrtl._
 import firrtl.ir._
-import firrtl.Utils._
-import firrtl.passes.MemPortUtils.{memPortField, memType}
-import Utils._
+import firrtl.passes.MemPortUtils.memPortField
 
 class SynFlopsPass(synflops: Boolean, libs: Seq[Macro]) extends firrtl.passes.Pass {
   val extraMods = scala.collection.mutable.ArrayBuffer.empty[Module]

macros/src/main/scala/barstools/macros/Utils.scala

@@ -2,14 +2,12 @@
 
 package barstools.macros
 
-import firrtl._
-import firrtl.ir._
-import firrtl.PrimOps
-import firrtl.passes.memlib.{MemConf, MemPort, ReadPort, WritePort, ReadWritePort, MaskedWritePort, MaskedReadWritePort}
 import firrtl.Utils.BoolType
-import mdf.macrolib.{Constant, MacroPort, SRAMMacro}
-import mdf.macrolib.{PolarizedPort, PortPolarity, ActiveLow, ActiveHigh, NegativeEdge, PositiveEdge, MacroExtraPort}
-import java.io.File
+import firrtl.ir._
+import firrtl.passes.memlib._
+import firrtl.{PrimOps, _}
+import mdf.macrolib.{Input => _, Output => _, _}
+
 import scala.language.implicitConversions
 
 object MacroCompilerMath {

macros/src/test/scala/barstools/macros/MacroCompilerSpec.scala

@@ -2,14 +2,13 @@
 
 package barstools.macros
 
+import firrtl.Parser.parse
 import firrtl.ir.{Circuit, NoInfo}
 import firrtl.passes.RemoveEmpty
-import firrtl.Parser.parse
-
-import java.io.{File, StringWriter}
-
 import mdf.macrolib.SRAMMacro
 
+import java.io.File
+
 abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalatest.Matchers {
   import scala.language.implicitConversions
   implicit def String2SomeString(i: String): Option[String] = Some(i)
@@ -122,6 +121,7 @@ abstract class MacroCompilerSpec extends org.scalatest.FlatSpec with org.scalate
 // A collection of standard SRAM generators.
 trait HasSRAMGenerator {
   import mdf.macrolib._
+
   import scala.language.implicitConversions
   implicit def Int2SomeInt(i: Int): Option[Int] = Some(i)
   implicit def BigInt2SomeBigInt(i: BigInt): Option[BigInt] = Some(i)

macros/src/test/scala/barstools/macros/Masks.scala

@@ -1,7 +1,5 @@
 package barstools.macros
 
-import mdf.macrolib._
-
 // Test the ability of the compiler to deal with various mask combinations.
 
 trait MasksTestSettings {

macros/src/test/scala/barstools/macros/SRAMCompiler.scala

@@ -1,7 +1,5 @@
 package barstools.macros
 
-import mdf.macrolib._
-
 class SRAMCompiler extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
   val compiler = generateSRAMCompiler("awesome", "A")
   val verilog = s"v-SRAMCompiler.v"

macros/src/test/scala/barstools/macros/SimpleSplitDepth.scala

@@ -1,7 +1,5 @@
 package barstools.macros
 
-import mdf.macrolib._
-
 // Test the depth splitting aspect of the memory compiler.
 // This file is for simple tests: one read-write port, powers of two sizes, etc.
 // For example, implementing a 4096x32 memory using four 1024x32 memories.

tapeout/src/main/scala/barstools/tapeout/transforms/AddSuffixToModuleNames.scala

@@ -2,12 +2,12 @@
 
 package barstools.tapeout.transforms
 
-import firrtl._
-import firrtl.ir._
 import firrtl.Mappers._
-import firrtl.annotations.{ModuleTarget, SingleTargetAnnotation, CircuitTarget}
-import firrtl.stage.TransformManager.{TransformDependency}
-import firrtl.stage.{Forms}
+import firrtl._
+import firrtl.annotations.{CircuitTarget, ModuleTarget, SingleTargetAnnotation}
+import firrtl.ir._
+import firrtl.stage.Forms
+import firrtl.stage.TransformManager.TransformDependency
 
 case class KeepNameAnnotation(target: ModuleTarget)
     extends SingleTargetAnnotation[ModuleTarget] {

tapeout/src/main/scala/barstools/tapeout/transforms/AvoidExtModuleCollisions.scala

@@ -3,12 +3,12 @@
 package barstools.tapeout.transforms
 
 import firrtl._
+import firrtl.annotations.NoTargetAnnotation
 import firrtl.ir._
-import firrtl.annotations.{NoTargetAnnotation}
-import firrtl.options.{Dependency}
-import firrtl.stage.TransformManager.{TransformDependency}
-import firrtl.stage.{Forms}
-import firrtl.passes.memlib.{ReplSeqMem}
+import firrtl.options.Dependency
+import firrtl.passes.memlib.ReplSeqMem
+import firrtl.stage.Forms
+import firrtl.stage.TransformManager.TransformDependency
 
 case class LinkExtModulesAnnotation(mustLink: Seq[ExtModule]) extends NoTargetAnnotation
 

tapeout/src/main/scala/barstools/tapeout/transforms/ConvertToExtModPass.scala

@@ -3,12 +3,12 @@
 package barstools.tapeout.transforms
 
 import firrtl._
+import firrtl.annotations.{ModuleTarget, ReferenceTarget, SingleTargetAnnotation}
 import firrtl.ir._
-import firrtl.annotations.{ModuleTarget, SingleTargetAnnotation, ReferenceTarget}
-import firrtl.stage.TransformManager.{TransformDependency}
-import firrtl.stage.{Forms}
-import firrtl.options.{Dependency}
-import firrtl.passes.memlib.{ReplSeqMem}
+import firrtl.options.Dependency
+import firrtl.passes.memlib.ReplSeqMem
+import firrtl.stage.Forms
+import firrtl.stage.TransformManager.TransformDependency
 
 case class ConvertToExtModAnnotation(target: ModuleTarget)
     extends SingleTargetAnnotation[ModuleTarget] {

tapeout/src/main/scala/barstools/tapeout/transforms/Generate.scala

@@ -5,7 +5,7 @@ import firrtl.annotations._
 import firrtl.ir._
 import firrtl.passes.memlib.ReplSeqMemAnnotation
 import firrtl.stage.FirrtlCircuitAnnotation
-import firrtl.transforms.{BlackBoxResourceFileNameAnno, DedupModules}
+import firrtl.transforms.BlackBoxResourceFileNameAnno
 import logger.LazyLogging
 
 trait HasTapeoutOptions { self: ExecutionOptionsManager with HasFirrtlOptions =>

tapeout/src/main/scala/barstools/tapeout/transforms/ReParentCircuit.scala

@@ -3,11 +3,10 @@
 package barstools.tapeout.transforms
 
 import firrtl._
-import firrtl.ir._
 import firrtl.annotations._
-import firrtl.options.{Dependency}
-import firrtl.stage.TransformManager.{TransformDependency}
-import firrtl.stage.{Forms}
+import firrtl.options.Dependency
+import firrtl.stage.Forms
+import firrtl.stage.TransformManager.TransformDependency
 
 case class ReParentCircuitAnnotation(target: ModuleTarget)
     extends SingleTargetAnnotation[ModuleTarget] {

tapeout/src/main/scala/barstools/tapeout/transforms/RemoveUnusedModules.scala

@@ -3,12 +3,12 @@
 package barstools.tapeout.transforms
 
 import firrtl._
+import firrtl.annotations.ModuleTarget
 import firrtl.ir._
-import firrtl.annotations.{ModuleTarget}
-import firrtl.stage.TransformManager.{TransformDependency}
-import firrtl.options.{Dependency}
-import firrtl.stage.{Forms}
-import firrtl.passes.memlib.{ReplSeqMem}
+import firrtl.options.Dependency
+import firrtl.passes.memlib.ReplSeqMem
+import firrtl.stage.Forms
+import firrtl.stage.TransformManager.TransformDependency
 
 // Removes all the unused modules in a circuit by recursing through every
 // instance (starting at the main module)

tapeout/src/test/scala/barstools/tapeout/transforms/ResetInverterSpec.scala

@@ -3,7 +3,7 @@
 package barstools.tapeout.transforms
 
 import chisel3._
-import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}
+import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
 import firrtl.{EmittedFirrtlCircuitAnnotation, EmittedFirrtlModuleAnnotation}
 import org.scalatest.{FreeSpec, Matchers}
 

tapeout/src/test/scala/barstools/tapeout/transforms/retime/RetimeSpec.scala

@@ -1,12 +1,10 @@
 // See LICENSE for license details.
 
-package barstools.tapeout.transforms.retime.test
+package barstools.tapeout.transforms.retime
 
 import chisel3._
-import chisel3.stage.{ChiselStage, ChiselGeneratorAnnotation}
-import firrtl.{EmittedFirrtlCircuitAnnotation, EmittedFirrtlModuleAnnotation}
-import barstools.tapeout.transforms.retime.RetimeLib
-import firrtl.FileUtils
+import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
+import firrtl.{EmittedFirrtlCircuitAnnotation, EmittedFirrtlModuleAnnotation, FileUtils}
 import logger.Logger
 import org.scalatest.{FlatSpec, Matchers}