wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Update FireChip with the new locations for subsystem

Browse Source
This commit is contained in:
Jerry Zhao
2019-08-26 14:51:20 -07:00
parent ba3deac1de
commit 19282fd438
3 changed files with 8 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
generators/firechip/src/main/scala/Generator.scala
View File

@@ -27,8 +27,8 @@ trait HasTestSuites {
"rv64ud-v-fadd", "rv64ud-v-fadd",
"rv64uf-v-fadd", "rv64uf-v-fadd",
"rv64um-v-mul", "rv64um-v-mul",
// "rv64mi-p-breakpoint", // Not implemented in BOOM "rv64mi-p-breakpoint",
// "rv64uc-v-rvc", // Not implemented in BOOM "rv64uc-v-rvc",
"rv64ud-v-structural", "rv64ud-v-structural",
"rv64si-p-wfi", "rv64si-p-wfi",
"rv64um-v-divw", "rv64um-v-divw",

2
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -9,7 +9,7 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.subsystem._ import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.tilelink.BootROMParams
import freechips.rocketchip.devices.debug.DebugModuleParams import freechips.rocketchip.devices.debug.DebugModuleParams
import boom.system.BoomTilesKey import boom.common.BoomTilesKey
import testchipip.{WithBlockDevice, BlockDeviceKey, BlockDeviceConfig} import testchipip.{WithBlockDevice, BlockDeviceKey, BlockDeviceConfig}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import icenet._ import icenet._

10
generators/firechip/src/main/scala/Targets.scala
View File

@@ -11,7 +11,7 @@ import freechips.rocketchip.util.{HeterogeneousBag}
import freechips.rocketchip.amba.axi4.AXI4Bundle import freechips.rocketchip.amba.axi4.AXI4Bundle
import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.diplomacy.LazyModule
import boom.system.{BoomRocketSubsystem, BoomRocketSubsystemModuleImp} import example.{Subsystem, SubsystemModuleImp}
import icenet._ import icenet._
import testchipip._ import testchipip._
import testchipip.SerialAdapter.SERIAL_IF_WIDTH import testchipip.SerialAdapter.SERIAL_IF_WIDTH
@@ -80,7 +80,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod
with HasTraceIOImp with HasTraceIOImp
class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem class FireBoom(implicit p: Parameters) extends Subsystem
with HasHierarchicalBusTopology with HasHierarchicalBusTopology
with CanHaveFASEDOptimizedMasterAXI4MemPort with CanHaveFASEDOptimizedMasterAXI4MemPort
with HasPeripheryBootROM with HasPeripheryBootROM
@@ -94,7 +94,7 @@ class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem
override lazy val module = new FireBoomModuleImp(this) override lazy val module = new FireBoomModuleImp(this)
} }
class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleImp(l) class FireBoomModuleImp[+L <: FireBoom](l: L) extends SubsystemModuleImp(l)
with HasRTCModuleImp with HasRTCModuleImp
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
with HasPeripheryBootROMModuleImp with HasPeripheryBootROMModuleImp
@@ -106,7 +106,7 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleI
with HasTraceIOImp with HasTraceIOImp
with ExcludeInvalidBoomAssertions with ExcludeInvalidBoomAssertions
class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem class FireBoomNoNIC(implicit p: Parameters) extends Subsystem
with HasHierarchicalBusTopology with HasHierarchicalBusTopology
with CanHaveFASEDOptimizedMasterAXI4MemPort with CanHaveFASEDOptimizedMasterAXI4MemPort
with HasPeripheryBootROM with HasPeripheryBootROM
@@ -119,7 +119,7 @@ class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem
override lazy val module = new FireBoomNoNICModuleImp(this) override lazy val module = new FireBoomNoNICModuleImp(this)
} }
class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomRocketSubsystemModuleImp(l) class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends SubsystemModuleImp(l)
with HasRTCModuleImp with HasRTCModuleImp
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
with HasPeripheryBootROMModuleImp with HasPeripheryBootROMModuleImp