wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Add RocketDummyVortexConfig

Browse Source
This commit is contained in:
Hansung Kim
2023-12-12 02:22:34 -08:00
parent 103c3afd0d
commit 18c5e55eb2
1 changed files with 46 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

49
generators/chipyard/src/main/scala/config/RocketConfigs.scala
View File

@@ -35,6 +35,19 @@ class WithRadBootROM(address: BigInt = 0x10000, size: Int = 0x10000, hang: BigIn
)) ))
}) })
class RocketDummyVortexConfig extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
new WithExtMemSize(BigInt("80000000", 16)) ++
new testchipip.WithMbusScratchpad(base=0x7FFF0000L, size=0x10000, banks=1) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
new AbstractConfig)
class RadianceROMConfig extends Config( class RadianceROMConfig extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++ new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++ new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++
@@ -49,13 +62,28 @@ class RadianceROMConfig extends Config(
new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++ new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++
new AbstractConfig) new AbstractConfig)
class RadianceROMNoCoalConfig extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++
// new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16, enable = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
// new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
new WithExtMemSize(BigInt("80000000", 16)) ++
new WithRadBootROM() ++
new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++
new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++
new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++
new AbstractConfig)
class RadianceROMLargeConfig extends Config( class RadianceROMLargeConfig extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores(4, useVxCache = false) ++ new freechips.rocketchip.subsystem.WithRadianceCores(4, useVxCache = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++ new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++ new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
// new freechips.rocketchip.subsystem.WithNBanks(4) ++ // new freechips.rocketchip.subsystem.WithNBanks(4) ++
new chipyard.config.WithSystemBusWidth(bitWidth = 512) ++ new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
new WithExtMemSize(BigInt("80000000", 16)) ++ new WithExtMemSize(BigInt("80000000", 16)) ++
new WithRadBootROM() ++ new WithRadBootROM() ++
new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++ new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++
@@ -64,10 +92,25 @@ class RadianceROMLargeConfig extends Config(
new AbstractConfig) new AbstractConfig)
class RadianceROMCacheConfig extends Config( class RadianceROMCacheConfig extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores(8, useVxCache = false) ++ new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++ new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++ new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++
new freechips.rocketchip.subsystem.WithVortexL1Banks(nBanks = 4)++ new freechips.rocketchip.subsystem.WithVortexL1Banks(nBanks = 1)++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
new WithExtMemSize(BigInt("80000000", 16)) ++
new WithRadBootROM() ++
new WithRadROMs(0x7FFF0000L, 0x10000, "sims/args.bin") ++
new WithRadROMs(0x20000L, 0x8000, "sims/op_a.bin") ++
new WithRadROMs(0x28000L, 0x8000, "sims/op_b.bin") ++
new AbstractConfig)
class RadianceROMCacheNoCoalConfig extends Config(
new freechips.rocketchip.subsystem.WithRadianceCores(1, useVxCache = false) ++
// new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16, enable = false) ++
new freechips.rocketchip.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new freechips.rocketchip.subsystem.WithSimtLanes(nLanes = 4, nSrcIds = 16) ++
new freechips.rocketchip.subsystem.WithVortexL1Banks(nBanks = 1)++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++ new chipyard.config.WithSystemBusWidth(bitWidth = 256) ++
new WithExtMemSize(BigInt("80000000", 16)) ++ new WithExtMemSize(BigInt("80000000", 16)) ++