[docs] update documentation [ci skip] (#393)

docs/Customization/Memory-Hierarchy.rst

@@ -15,18 +15,24 @@ configure 4 KiB direct-mapped caches for L1I and L1D.
 .. code-block:: scala
 
     class SmallRocketConfig extends Config(
-        new WithTop ++                                       // use default top
-        new WithBootROM ++                                   // use default bootrom
-        new freechips.rocketchip.subsystem.WithNSmallCores(1) ++
+        new WithTSI ++
+        new WithNoGPIO ++
+        new WithBootROM ++
+        new WithUART ++
+        new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+        new freechips.rocketchip.subsystem.WithNoSlavePort ++
+        new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // small rocket cores
         new freechips.rocketchip.system.BaseConfig)
 
-    class SmallRocketConfig extends Config(
-        new freechips.rocketchip.subsystem.WithNSmallCores(1) ++
-        new RocketConfig)
-
     class MediumRocketConfig extends Config(
-        new freechips.rocketchip.subsystem.WithNMedCores(1) ++
-        new RocketConfig)
+        new WithTSI ++
+        new WithNoGPIO ++
+        new WithBootROM ++
+        new WithUART ++
+        new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+        new freechips.rocketchip.subsystem.WithNoSlavePort ++
+        new freechips.rocketchip.subsystem.WithNMedCores(1) ++ // medium rocket cores
+        new freechips.rocketchip.system.BaseConfig)
 
 If you only want to change the size or associativity, there are configuration
 mixins for those too.
@@ -36,11 +42,18 @@ mixins for those too.
     import freechips.rocketchip.subsystem.{WithL1ICacheSets, WithL1DCacheSets, WithL1ICacheWays, WithL1DCacheWays}
 
     class MyL1RocketConfig extends Config(
-        new WithL1ICacheSets(128) ++
-        new WithL1ICacheWays(2) ++
-        new WithL1DCacheSets(128) ++
-        new WithL1DCacheWays(2) ++
-        new RocketConfig)
+        new WithTSI ++
+        new WithNoGPIO ++
+        new WithBootROM ++
+        new WithUART ++
+        new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+        new freechips.rocketchip.subsystem.WithNoSlavePort ++
+        new WithL1ICacheSets(128) ++                              // change rocket I$
+        new WithL1ICacheWays(2) ++                                // change rocket I$
+        new WithL1DCacheSets(128) ++                              // change rocket D$
+        new WithL1DCacheWays(2) ++                                // change rocket D$
+        new freechips.rocketchip.subsystem.WithNSmallCores(1) ++
+        new freechips.rocketchip.system.BaseConfig)
 
 You can also configure the L1 data cache as an data scratchpad instead.
 However, there are some limitations on this. If you are using a data scratchpad,
@@ -49,18 +62,22 @@ Note that these configurations fully remove the L2 cache and mbus.
 
 .. code-block:: scala
 
-    class SmallRocketConfigNoL2 extends Config( 
-        new WithTop ++                              // use default top 
-        new WithBootROM ++                          // use default bootrom 
-        new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ 
-        new freechips.rocketchip.system.BaseConfig)          
-                                                
+    class SmallRocketConfigNoL2 extends Config(
+        new WithTSI ++
+        new WithNoGPIO ++
+        new WithBootROM ++
+        new WithUART ++
+        new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+        new freechips.rocketchip.subsystem.WithNoSlavePort ++
+        new freechips.rocketchip.subsystem.WithNSmallCores(1) ++
+        new freechips.rocketchip.system.BaseConfig)
+
     class ScratchpadRocketConfig extends Config(
-        new freechips.rocketchip.subsystem.WithNoMemPort ++ 
-        new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ 
-        new freechips.rocketchip.subsystem.WithNBanks(0) ++ 
-        new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ 
-        new SmallRocketConfigNoL2) 
+        new freechips.rocketchip.subsystem.WithNoMemPort ++
+        new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
+        new freechips.rocketchip.subsystem.WithNBanks(0) ++
+        new freechips.rocketchip.subsystem.WithScratchpadsOnly ++
+        new SmallRocketConfigNoL2)
 
 This configuration fully removes the L2 cache and memory bus by setting the
 number of channels and number of banks to 0.
@@ -79,13 +96,19 @@ and the number of banks must be powers of 2.
 
     import freechips.rocketchip.subsystem.WithInclusiveCache
 
-    # Create an SoC with 1 MB, 4-way, 4-bank cache
     class MyCacheRocketConfig extends Config(
-        new WithInclusiveCache(
+        new WithTSI ++
+        new WithNoGPIO ++
+        new WithBootROM ++
+        new WithUART ++
+        new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+        new freechips.rocketchip.subsystem.WithNoSlavePort ++
+        new WithInclusiveCache(                                // add 1MB, 4-way, 4-bank cache
             capacityKB = 1024,
             nWays = 4,
             nBanks = 4) ++
-        new RocketConfig)
+        new freechips.rocketchip.subsystem.WithNSmallCores(1) ++
+        new freechips.rocketchip.system.BaseConfig)
 
 The Broadcast Hub
 -----------------
@@ -99,13 +122,15 @@ list of included mixims.
 
 .. code-block:: scala
 
-    import freechips.rocketchip.subsystem.{WithNBigCores, BaseConfig}
-
     class CachelessRocketConfig extends Config(
-        new WithTop ++
+        new WithTSI ++
+        new WithNoGPIO ++
         new WithBootROM ++
-        new WithNBigCores(1) ++
-        new BaseConfig)
+        new WithUART ++
+        new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+        new freechips.rocketchip.subsystem.WithNoSlavePort ++
+        new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+        new freechips.rocketchip.system.BaseConfig)
 
 If you want to reduce the resources used even further, you can configure
 the Broadcast Hub to use a bufferless design.
@@ -133,8 +158,15 @@ number of DRAM channels is restricted to powers of two.
     import freechips.rocketchip.subsystem.WithNMemoryChannels
 
     class DualChannelRocketConfig extends Config(
-        new WithNMemoryChannels(2) ++
-        new RocketConfig)
+        new WithTSI ++
+        new WithNoGPIO ++
+        new WithBootROM ++
+        new WithUART ++
+        new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+        new freechips.rocketchip.subsystem.WithNoSlavePort ++
+        new WithNMemoryChannels(2) ++                          // multi-channel outer mem
+        new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+        new freechips.rocketchip.system.BaseConfig)
 
 In VCS and Verilator simulation, the DRAM is simulated using the
 ``SimAXIMem`` module, which simply attaches a single-cycle SRAM to each