diff --git a/src/main/scala/example/TestHarness.scala b/src/main/scala/example/TestHarness.scala
index dfff7e26..a5af6240 100644
--- a/src/main/scala/example/TestHarness.scala
+++ b/src/main/scala/example/TestHarness.scala
@@ -39,5 +39,6 @@ object Generator extends GeneratorApp {
   val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
   generateFirrtl
   generateAnno
+  generateTestSuiteMakefrags
   generateArtefacts
 }
diff --git a/verisim/Makefile b/verisim/Makefile
index 69ecad27..dc3a219e 100644
--- a/verisim/Makefile
+++ b/verisim/Makefile
@@ -22,6 +22,9 @@ LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesv
 
 include $(base_dir)/Makefrag
 include $(sim_dir)/Makefrag-verilator
+ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
+-include $(build_dir)/$(long_name).d
+endif
 
 sim_blackboxes = \
   $(build_dir)/firrtl_black_box_resource_files.f
diff --git a/vsim/Makefile b/vsim/Makefile
index 2f6a8488..bd8afc29 100644
--- a/vsim/Makefile
+++ b/vsim/Makefile
@@ -18,6 +18,9 @@ default: $(simv)
 debug: $(simv_debug)
 
 include $(base_dir)/Makefrag
+ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
+-include $(build_dir)/$(long_name).d
+endif
 
 sim_blackboxes = \
   $(build_dir)/firrtl_black_box_resource_files.f