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Update spike-as-a-tile docs

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Jerry Zhao
2023-03-30 23:55:08 -07:00
parent 8cb97bff85
commit 162ceca9ab
1 changed files with 17 additions and 0 deletions
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docs/Software/Spike.rst
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@@ -32,4 +32,21 @@ In this configuration, Spike is cache-coherent, and communicates with the uncore
make CONFIG=SpikeConfig run-binary BINARY=hello.riscv make CONFIG=SpikeConfig run-binary BINARY=hello.riscv
Spike-as-a-Tile also supports Tightly-Coupled-Memory (TCM) for the SpikeTile, in which the main system memory is entirely modeled
within the Spike tile, allowing for very fast simulatoin performance.
.. code-block:: shell
make CONFIG=SpikeUltraFastConfig run-binary BINARY=hello.riscv
Spike-as-a-Tile can be configure with custom IPC, commit logging, and other behaviors. Spike-specific flags can be added as plusargs to ``EXTRA_SIM_FLAGS``
.. code-block:: shell
make CONFIG=SpikeUltraFastConfig run-binary-hex BINARY=hello.riscv EXTRA_SPIKE_FLAGS="+spike-ipc=10000 +spike-fast-clint +spike-debug"
* ``+spike-ipc=``: Sets the maximum number of instructions Spike can retire in a single "tick", or cycle of the uncore simulation.
* ``+spike-fast-clint``: Enables fast-forwrding through WFI stalls by generating fake timer interrupts
* ``+spike-debug``: Enables debug spike logging
* ``+spike-verbose``: Enabbls spike commit-log generation