Fix all warnings in barstool.macros._

- Fixed up all warnings in barstools macros package - mostly public method return types - removed lot's of extraneous parens and braces - Made code cleaner using more explicit macros - Fixed warnings in 2.13 that will likely turn into errors in future
2021-08-17 16:09:52 -07:00
parent edb1537561
commit 143af1aa04
15 changed files with 500 additions and 516 deletions
--- a/src/test/scala/barstools/macros/CostFunction.scala
+++ b/src/test/scala/barstools/macros/CostFunction.scala
@@ -11,9 +11,9 @@ object TestMinWidthMetric extends CostMetric with CostMetricCompanion {
  // Smaller width = lower cost = favoured
  override def cost(mem: Macro, lib: Macro): Option[Double] = Some(lib.src.width)

-  override def commandLineParams = Map()
-  override def name = "TestMinWidthMetric"
-  override def construct(m: Map[String, String]) = TestMinWidthMetric
+  override def commandLineParams() = Map()
+  override def name() = "TestMinWidthMetric"
+  override def construct(m: Map[String, String]): CostMetric = TestMinWidthMetric
 }

 /** Test that cost metric selection is working. */
@@ -25,7 +25,7 @@ class SelectCostMetric extends MacroCompilerSpec with HasSRAMGenerator {
  // Cost metrics must be registered for them to work with the command line.
  CostMetric.registerCostMetric(TestMinWidthMetric)

-  override val costMetric = Some(TestMinWidthMetric)
+  override val costMetric: Option[CostMetric] = Some(TestMinWidthMetric)

  val libSRAMs = Seq(
    SRAMMacro(
--- a/src/test/scala/barstools/macros/Functional.scala
+++ b/src/test/scala/barstools/macros/Functional.scala
@@ -1,5 +1,6 @@
 package barstools.macros

+import firrtl.ir.Circuit
 import firrtl_interpreter.InterpretiveTester

 // Functional tests on memory compiler outputs.
@@ -10,8 +11,8 @@ class SynchronousReadAndWrite extends MacroCompilerSpec with HasSRAMGenerator wi
  override lazy val memDepth = BigInt(2048)
  override lazy val libDepth = BigInt(1024)

-  compile(mem, lib, v, true)
-  val result = execute(mem, lib, true)
+  compile(mem, lib, v, synflops = true)
+  val result: Circuit = execute(mem, lib, synflops = true)

  it should "run with InterpretedTester" in {
    pending // Enable this when https://github.com/freechipsproject/firrtl-interpreter/pull/88 is snapshot-published
@@ -70,8 +71,8 @@ class DontReadCombinationally extends MacroCompilerSpec with HasSRAMGenerator wi
  override lazy val memDepth = BigInt(2048)
  override lazy val libDepth = BigInt(1024)

-  compile(mem, lib, v, true)
-  val result = execute(mem, lib, true)
+  compile(mem, lib, v, synflops = true)
+  val result: Circuit = execute(mem, lib, synflops = true)

  it should "run with InterpretedTester" in {
    pending // Enable this when https://github.com/freechipsproject/firrtl-interpreter/pull/88 is snapshot-published
--- a/src/test/scala/barstools/macros/MacroCompilerSpec.scala
+++ b/src/test/scala/barstools/macros/MacroCompilerSpec.scala
@@ -31,19 +31,18 @@ abstract class MacroCompilerSpec extends AnyFlatSpec with Matchers {
  private def costMetricCmdLine = {
    costMetric match {
      case None => Nil
-      case Some(m) => {
-        val name = m.name
-        val params = m.commandLineParams
+      case Some(m) =>
+        val name = m.name()
+        val params = m.commandLineParams()
        List("-c", name) ++ params.flatMap { case (key, value) => List("-cp", key, value) }
-      }
    }
  }

  private def args(mem: String, lib: Option[String], v: String, synflops: Boolean, useCompiler: Boolean) =
-    List("-m", mem.toString, "-v", v) ++
+    List("-m", mem, "-v", v) ++
      (lib match {
        case None    => Nil
-        case Some(l) => List("-l", l.toString)
+        case Some(l) => List("-l", l)
      }) ++
      costMetricCmdLine ++
      (if (synflops) List("--mode", "synflops") else Nil) ++
@@ -52,23 +51,23 @@ abstract class MacroCompilerSpec extends AnyFlatSpec with Matchers {
  // Run the full compiler as if from the command line interface.
  // Generates the Verilog; useful in testing since an error will throw an
  // exception.
-  def compile(mem: String, lib: String, v: String, synflops: Boolean) {
+  def compile(mem: String, lib: String, v: String, synflops: Boolean): Unit = {
    compile(mem, Some(lib), v, synflops)
  }
-  def compile(mem: String, lib: Option[String], v: String, synflops: Boolean, useCompiler: Boolean = false) {
-    var mem_full = concat(memPrefix, mem)
-    var lib_full = concat(libPrefix, lib)
-    var v_full = concat(vPrefix, v)
+  def compile(mem: String, lib: Option[String], v: String, synflops: Boolean, useCompiler: Boolean = false): Unit = {
+    val mem_full = concat(memPrefix, mem)
+    val lib_full = concat(libPrefix, lib)
+    val v_full = concat(vPrefix, v)

    MacroCompiler.run(args(mem_full, lib_full, v_full, synflops, useCompiler))
  }

  // Helper functions to write macro libraries to the given files.
-  def writeToLib(lib: String, libs: Seq[mdf.macrolib.Macro]) = {
+  def writeToLib(lib: String, libs: Seq[mdf.macrolib.Macro]): Boolean = {
    mdf.macrolib.Utils.writeMDFToPath(Some(concat(libPrefix, lib)), libs)
  }

-  def writeToMem(mem: String, mems: Seq[mdf.macrolib.Macro]) = {
+  def writeToMem(mem: String, mems: Seq[mdf.macrolib.Macro]): Boolean = {
    mdf.macrolib.Utils.writeMDFToPath(Some(concat(memPrefix, mem)), mems)
  }

@@ -89,16 +88,16 @@ abstract class MacroCompilerSpec extends AnyFlatSpec with Matchers {
  // Compare FIRRTL outputs after reparsing output with ScalaTest ("should be").
  def test(result: Circuit, output: String): Unit = {
    val gold = RemoveEmpty.run(parse(output))
-    (result.serialize) should be(gold.serialize)
+    result.serialize should be(gold.serialize)
  }

  // Execute the macro compiler and returns a Circuit containing the output of
  // the memory compiler.
  def execute(memFile: Option[String], libFile: Option[String], synflops: Boolean): Circuit =
-    execute(memFile, libFile, synflops, false)
+    execute(memFile, libFile, synflops, useCompiler = false)
  def execute(memFile: Option[String], libFile: Option[String], synflops: Boolean, useCompiler: Boolean): Circuit = {
-    var mem_full = concat(memPrefix, memFile)
-    var lib_full = concat(libPrefix, libFile)
+    val mem_full = concat(memPrefix, memFile)
+    val lib_full = concat(libPrefix, libFile)

    require(memFile.isDefined)
    val mems: Seq[Macro] = Utils.filterForSRAM(mdf.macrolib.Utils.readMDFFromPath(mem_full)).get.map(new Macro(_))
@@ -126,7 +125,7 @@ abstract class MacroCompilerSpec extends AnyFlatSpec with Matchers {
      new SynFlopsPass(synflops, libs.getOrElse(mems)),
      RemoveEmpty
    )
-    val result: Circuit = (passes.foldLeft(circuit))((c, pass) => pass.run(c))
+    val result: Circuit = passes.foldLeft(circuit)((c, pass) => pass.run(c))
    result
  }

@@ -171,7 +170,7 @@ trait HasSRAMGenerator {
      output = if (read) Some(PolarizedPort(name = realPrefix + "dout", polarity = ActiveHigh)) else None,
      input = if (write) Some(PolarizedPort(name = realPrefix + "din", polarity = ActiveHigh)) else None,
      maskPort = maskGran match {
-        case Some(x: Int) => Some(PolarizedPort(name = realPrefix + "mask", polarity = ActiveHigh))
+        case Some(_: Int) => Some(PolarizedPort(name = realPrefix + "mask", polarity = ActiveHigh))
        case _ => None
      },
      maskGran = maskGran,
@@ -208,16 +207,7 @@ trait HasSRAMGenerator {
    depth:    Option[BigInt],
    maskGran: Option[Int] = None
  ): MacroPort = {
-    generateTestPort(
-      prefix,
-      width,
-      depth,
-      maskGran = maskGran,
-      write = true,
-      writeEnable = true,
-      read = true,
-      readEnable = false
-    )
+    generateTestPort(prefix, width, depth, maskGran = maskGran, write = true, writeEnable = true, read = true)
  }

  // Generate a "simple" SRAM (active high/positive edge, 1 read-write port).
@@ -241,12 +231,11 @@ trait HasSRAMGenerator {

  // Generate a "simple" SRAM group (active high/positive edge, 1 read-write port).
  def generateSimpleSRAMGroup(
-    prefix:     String,
-    mux:        Int,
-    depth:      Range,
-    width:      Range,
-    maskGran:   Option[Int] = None,
-    extraPorts: Seq[MacroExtraPort] = List()
+    prefix:   String,
+    mux:      Int,
+    depth:    Range,
+    width:    Range,
+    maskGran: Option[Int] = None
  ): SRAMGroup = {
    SRAMGroup(
      Seq("mygroup_", "width", "x", "depth", "_", "VT"),
@@ -291,7 +280,7 @@ trait HasSimpleTestGenerator {
  def extraTag:    String = ""

  // "Effective" libMaskGran by considering write_enable.
-  val effectiveLibMaskGran = libMaskGran.getOrElse(libWidth)
+  val effectiveLibMaskGran: Int = libMaskGran.getOrElse(libWidth)

  // Override this in the sub-generator if you need a more specific name.
  // Defaults to using reflection to pull the name of the test using this
@@ -301,23 +290,23 @@ trait HasSimpleTestGenerator {
  //require (memDepth >= libDepth)

  // Convenience variables to check if a mask exists.
-  val memHasMask = memMaskGran != None
-  val libHasMask = libMaskGran != None
+  val memHasMask: Boolean = memMaskGran.isDefined
+  val libHasMask: Boolean = libMaskGran.isDefined
  // We need to figure out how many mask bits there are in the mem.
-  val memMaskBits = if (memHasMask) memWidth / memMaskGran.get else 0
-  val libMaskBits = if (libHasMask) libWidth / libMaskGran.get else 0
+  val memMaskBits: Int = if (memHasMask) memWidth / memMaskGran.get else 0
+  val libMaskBits: Int = if (libHasMask) libWidth / libMaskGran.get else 0

-  val extraTagPrefixed = if (extraTag == "") "" else ("-" + extraTag)
+  val extraTagPrefixed: String = if (extraTag == "") "" else "-" + extraTag

-  val mem = s"mem-${generatorType}${extraTagPrefixed}.json"
-  val lib = s"lib-${generatorType}${extraTagPrefixed}.json"
-  val v = s"${generatorType}${extraTagPrefixed}.v"
+  val mem = s"mem-$generatorType$extraTagPrefixed.json"
+  val lib = s"lib-$generatorType$extraTagPrefixed.json"
+  val v = s"$generatorType$extraTagPrefixed.v"

  lazy val mem_name = "target_memory"
-  val mem_addr_width = MacroCompilerMath.ceilLog2(memDepth)
+  val mem_addr_width: Int = MacroCompilerMath.ceilLog2(memDepth)

  lazy val lib_name = "awesome_lib_mem"
-  val lib_addr_width = MacroCompilerMath.ceilLog2(libDepth)
+  val lib_addr_width: Int = MacroCompilerMath.ceilLog2(libDepth)

  // Override these to change the port prefixes if needed.
  def libPortPrefix: String = "lib"
@@ -325,11 +314,11 @@ trait HasSimpleTestGenerator {

  // These generate "simple" SRAMs (1 masked read-write port) by default,
  // but can be overridden if need be.
-  def generateLibSRAM() = generateSRAM(lib_name, libPortPrefix, libWidth, libDepth, libMaskGran, extraPorts)
-  def generateMemSRAM() = generateSRAM(mem_name, memPortPrefix, memWidth, memDepth, memMaskGran)
+  def generateLibSRAM(): SRAMMacro = generateSRAM(lib_name, libPortPrefix, libWidth, libDepth, libMaskGran, extraPorts)
+  def generateMemSRAM(): SRAMMacro = generateSRAM(mem_name, memPortPrefix, memWidth, memDepth, memMaskGran)

-  def libSRAM = generateLibSRAM
-  def memSRAM = generateMemSRAM
+  def libSRAM: SRAMMacro = generateLibSRAM()
+  def memSRAM: SRAMMacro = generateMemSRAM()

  def libSRAMs: Seq[SRAMMacro] = Seq(libSRAM)
  def memSRAMs: Seq[SRAMMacro] = Seq(memSRAM)
@@ -340,18 +329,19 @@ trait HasSimpleTestGenerator {
  // For masks, width it's a bit tricky since we have to consider cases like
  // memMaskGran = 4 and libMaskGran = 8.
  // Consider the actually usable libWidth in cases like the above.
-  val usableLibWidth = if (memMaskGran.getOrElse(Int.MaxValue) < effectiveLibMaskGran) memMaskGran.get else libWidth
+  val usableLibWidth: Int =
+    if (memMaskGran.getOrElse(Int.MaxValue) < effectiveLibMaskGran) memMaskGran.get else libWidth

  // Number of lib instances needed to hold the mem, in both directions.
  // Round up (e.g. 1.5 instances = effectively 2 instances)
-  val depthInstances = math.ceil(memDepth.toFloat / libDepth.toFloat).toInt
-  val widthInstances = math.ceil(memWidth.toFloat / usableLibWidth).toInt
+  val depthInstances: Int = math.ceil(memDepth.toFloat / libDepth.toFloat).toInt
+  val widthInstances: Int = math.ceil(memWidth.toFloat / usableLibWidth).toInt

  // Number of width bits in the last width-direction memory.
  // e.g. if memWidth = 16 and libWidth = 8, this would be 8 since the last memory 0_1 has 8 bits of input width.
  // e.g. if memWidth = 9 and libWidth = 8, this would be 1 since the last memory 0_1 has 1 bit of input width.
-  lazy val lastWidthBits = if (memWidth % usableLibWidth == 0) usableLibWidth else (memWidth % usableLibWidth)
-  lazy val selectBits = mem_addr_width - lib_addr_width
+  lazy val lastWidthBits: Int = if (memWidth % usableLibWidth == 0) usableLibWidth else memWidth % usableLibWidth
+  lazy val selectBits:    Int = mem_addr_width - lib_addr_width

  /** Convenience function to generate a mask statement.
    * @param widthInst Width instance (mem_0_x)
@@ -369,25 +359,25 @@ trait HasSimpleTestGenerator {
      if (memMaskGran.isEmpty) {
        // If there is no memory mask, we should just turn all the lib mask
        // bits high.
-        s"""mem_${depthInst}_${widthInst}.lib_mask <= UInt<${libMaskBits}>("h${((1 << libMaskBits) - 1).toHexString}")"""
+        s"""mem_${depthInst}_$widthInst.lib_mask <= UInt<$libMaskBits>("h${((1 << libMaskBits) - 1).toHexString}")"""
      } else {
        // Calculate which bit of outer_mask contains the given bit.
        // e.g. if memMaskGran = 2, libMaskGran = 1 and libWidth = 4, then
        // calculateMaskBit({0, 1}) = 0 and calculateMaskBit({1, 2}) = 1
        def calculateMaskBit(bit: Int): Int = bit / memMaskGran.getOrElse(memWidth)

-        val bitsArr = ((libMaskBits - 1 to 0 by -1).map(x => {
+        val bitsArr = (libMaskBits - 1 to 0 by -1).map(x => {
          if (x * libMaskGran.get > myMemWidth) {
            // If we have extra mask bits leftover after the effective width,
            // disable those bits.
            """UInt<1>("h0")"""
          } else {
            val outerMaskBit = calculateMaskBit(x * libMaskGran.get + myBaseBit)
-            s"bits(outer_mask, ${outerMaskBit}, ${outerMaskBit})"
+            s"bits(outer_mask, $outerMaskBit, $outerMaskBit)"
          }
-        }))
+        })
        val maskVal = bitsArr.reduceRight((bit, rest) => s"cat($bit, $rest)")
-        s"mem_${depthInst}_${widthInst}.lib_mask <= ${maskVal}"
+        s"mem_${depthInst}_$widthInst.lib_mask <= $maskVal"
      }
    } else ""
  }
@@ -487,7 +477,7 @@ $extraPortsStr
    require(memSRAM.ports.size == 1, "Header generator only supports single RW port mem")
    generateReadWriteHeaderPort(
      memPortPrefix,
-      memSRAM.ports(0).readEnable.isDefined,
+      memSRAM.ports.head.readEnable.isDefined,
      if (memHasMask) Some(memMaskBits) else None
    )
  }
@@ -498,7 +488,7 @@ $extraPortsStr
    s"""
 circuit $mem_name :
  module $mem_name :
-${generateHeaderPorts}
+${generateHeaderPorts()}
  """
  }

@@ -507,7 +497,7 @@ ${generateHeaderPorts}
    require(libSRAM.ports.size == 1, "Footer generator only supports single RW port mem")
    generateReadWriteFooterPort(
      libPortPrefix,
-      libSRAM.ports(0).readEnable.isDefined,
+      libSRAM.ports.head.readEnable.isDefined,
      if (libHasMask) Some(libMaskBits) else None,
      extraPorts.map(p => (p.name, p.width))
    )
@@ -517,7 +507,7 @@ ${generateHeaderPorts}
  def generateFooter(): String = {
    s"""
  extmodule $lib_name :
-${generateFooterPorts}
+${generateFooterPorts()}

    defname = $lib_name
  """
@@ -529,13 +519,13 @@ ${generateFooterPorts}
  // Generate the entire output from header, body, and footer.
  def generateOutput(): String = {
    s"""
-${generateHeader}
-${generateBody}
-${generateFooter}
+${generateHeader()}
+${generateBody()}
+${generateFooter()}
      """
  }

-  val output = generateOutput()
+  val output: String = generateOutput()
 }

 // Use this trait for tests that invoke the memory compiler without lib.
@@ -545,12 +535,12 @@ trait HasNoLibTestGenerator extends HasSimpleTestGenerator {
  // If there isn't a lib, then the "lib" will become a FIRRTL "mem", which
  // in turn becomes synthesized flops.
  // Therefore, make "lib" width/depth equal to the mem.
-  override lazy val libDepth = memDepth
-  override lazy val libWidth = memWidth
-  override lazy val lib_name = mem_name
+  override lazy val libDepth: BigInt = memDepth
+  override lazy val libWidth: Int = memWidth
+  override lazy val lib_name: String = mem_name
  // Do the same for port names.
-  override lazy val libPortPrefix = memPortPrefix
+  override lazy val libPortPrefix: String = memPortPrefix

  // If there is no lib, don't generate a body.
-  override def generateBody = ""
+  override def generateBody() = ""
 }
--- a/src/test/scala/barstools/macros/Masks.scala
+++ b/src/test/scala/barstools/macros/Masks.scala
@@ -23,9 +23,9 @@ class Masks_FourTypes_NonMaskedMem_NonMaskedLib
    with HasSimpleWidthTestGenerator {
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 32
-  override lazy val memMaskGran = None
+  override lazy val memMaskGran: Option[Int] = None
  override lazy val libWidth = 8
-  override lazy val libMaskGran = None
+  override lazy val libMaskGran: Option[Int] = None

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -38,9 +38,9 @@ class Masks_FourTypes_NonMaskedMem_MaskedLib
    with HasSimpleWidthTestGenerator {
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 32
-  override lazy val memMaskGran = None
+  override lazy val memMaskGran: Option[Int] = None
  override lazy val libWidth = 8
-  override lazy val libMaskGran = Some(2)
+  override lazy val libMaskGran: Option[Int] = Some(2)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -53,9 +53,9 @@ class Masks_FourTypes_MaskedMem_NonMaskedLib
    with HasSimpleWidthTestGenerator {
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 32
-  override lazy val memMaskGran = Some(8)
+  override lazy val memMaskGran: Option[Int] = Some(8)
  override lazy val libWidth = 8
-  override lazy val libMaskGran = None
+  override lazy val libMaskGran: Option[Int] = None

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -68,9 +68,9 @@ class Masks_FourTypes_MaskedMem_NonMaskedLib_SmallerMaskGran
    with HasSimpleWidthTestGenerator {
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 32
-  override lazy val memMaskGran = Some(4)
+  override lazy val memMaskGran: Option[Int] = Some(4)
  override lazy val libWidth = 8
-  override lazy val libMaskGran = None
+  override lazy val libMaskGran: Option[Int] = None

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -83,9 +83,9 @@ class Masks_FourTypes_MaskedMem_MaskedLib
    with HasSimpleWidthTestGenerator {
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 32
-  override lazy val memMaskGran = Some(8)
+  override lazy val memMaskGran: Option[Int] = Some(8)
  override lazy val libWidth = 16
-  override lazy val libMaskGran = Some(4)
+  override lazy val libMaskGran: Option[Int] = Some(4)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -98,9 +98,9 @@ class Masks_FourTypes_MaskedMem_MaskedLib_SameMaskGran
    with HasSimpleWidthTestGenerator {
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 32
-  override lazy val memMaskGran = Some(8)
+  override lazy val memMaskGran: Option[Int] = Some(8)
  override lazy val libWidth = 16
-  override lazy val libMaskGran = Some(8)
+  override lazy val libMaskGran: Option[Int] = Some(8)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -113,9 +113,9 @@ class Masks_FourTypes_MaskedMem_MaskedLib_SmallerMaskGran
    with HasSimpleWidthTestGenerator {
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 64
-  override lazy val memMaskGran = Some(4)
+  override lazy val memMaskGran: Option[Int] = Some(4)
  override lazy val libWidth = 32
-  override lazy val libMaskGran = Some(8)
+  override lazy val libMaskGran: Option[Int] = Some(8)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -127,9 +127,9 @@ class Masks_FourTypes_MaskedMem_MaskedLib_SmallerMaskGran
 class Masks_BitMaskedMem_NonMaskedLib extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 16
-  override lazy val memMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(1)
  override lazy val libWidth = 8
-  override lazy val libMaskGran = None
+  override lazy val libMaskGran: Option[Int] = None

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -144,8 +144,8 @@ class Masks_FPGAStyle_32_8
    with HasSimpleDepthTestGenerator
    with MasksTestSettings {
  override lazy val width = 32
-  override lazy val memMaskGran = Some(32)
-  override lazy val libMaskGran = Some(8)
+  override lazy val memMaskGran: Option[Int] = Some(32)
+  override lazy val libMaskGran: Option[Int] = Some(8)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -160,8 +160,8 @@ class Masks_PowersOfTwo_8_1
    with HasSimpleDepthTestGenerator
    with MasksTestSettings {
  override lazy val width = 64
-  override lazy val memMaskGran = Some(8)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(8)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -174,8 +174,8 @@ class Masks_PowersOfTwo_16_1
    with HasSimpleDepthTestGenerator
    with MasksTestSettings {
  override lazy val width = 64
-  override lazy val memMaskGran = Some(16)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(16)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -188,8 +188,8 @@ class Masks_PowersOfTwo_32_1
    with HasSimpleDepthTestGenerator
    with MasksTestSettings {
  override lazy val width = 64
-  override lazy val memMaskGran = Some(32)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(32)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -202,8 +202,8 @@ class Masks_PowersOfTwo_64_1
    with HasSimpleDepthTestGenerator
    with MasksTestSettings {
  override lazy val width = 64
-  override lazy val memMaskGran = Some(64)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(64)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -218,8 +218,8 @@ class Masks_PowersOfTwo_32_4
    with HasSimpleDepthTestGenerator
    with MasksTestSettings {
  override lazy val width = 128
-  override lazy val memMaskGran = Some(32)
-  override lazy val libMaskGran = Some(4)
+  override lazy val memMaskGran: Option[Int] = Some(32)
+  override lazy val libMaskGran: Option[Int] = Some(4)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -232,8 +232,8 @@ class Masks_PowersOfTwo_32_8
    with HasSimpleDepthTestGenerator
    with MasksTestSettings {
  override lazy val width = 128
-  override lazy val memMaskGran = Some(32)
-  override lazy val libMaskGran = Some(8)
+  override lazy val memMaskGran: Option[Int] = Some(32)
+  override lazy val libMaskGran: Option[Int] = Some(8)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -246,8 +246,8 @@ class Masks_PowersOfTwo_8_8
    with HasSimpleDepthTestGenerator
    with MasksTestSettings {
  override lazy val width = 128
-  override lazy val memMaskGran = Some(8)
-  override lazy val libMaskGran = Some(8)
+  override lazy val memMaskGran: Option[Int] = Some(8)
+  override lazy val libMaskGran: Option[Int] = Some(8)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -262,8 +262,8 @@ class Masks_IntegerMaskMultiple_20_10
    with HasSimpleDepthTestGenerator
    with MasksTestSettings {
  override lazy val width = 20
-  override lazy val memMaskGran = Some(10)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(10)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -276,8 +276,8 @@ class Masks_IntegerMaskMultiple_21_7
    with HasSimpleDepthTestGenerator
    with MasksTestSettings {
  override lazy val width = 21
-  override lazy val memMaskGran = Some(21)
-  override lazy val libMaskGran = Some(7)
+  override lazy val memMaskGran: Option[Int] = Some(21)
+  override lazy val libMaskGran: Option[Int] = Some(7)

  (it should "be enabled when non-power of two masks are supported").is(pending)
  //~ compileExecuteAndTest(mem, lib, v, output)
@@ -289,8 +289,8 @@ class Masks_IntegerMaskMultiple_21_21
    with HasSimpleDepthTestGenerator
    with MasksTestSettings {
  override lazy val width = 21
-  override lazy val memMaskGran = Some(21)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(21)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -303,8 +303,8 @@ class Masks_IntegerMaskMultiple_84_21
    with HasSimpleDepthTestGenerator
    with MasksTestSettings {
  override lazy val width = 84
-  override lazy val memMaskGran = Some(21)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(21)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -317,8 +317,8 @@ class Masks_IntegerMaskMultiple_92_23
    with HasSimpleDepthTestGenerator
    with MasksTestSettings {
  override lazy val width = 92
-  override lazy val memMaskGran = Some(23)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(23)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -331,8 +331,8 @@ class Masks_IntegerMaskMultiple_117_13
    with HasSimpleDepthTestGenerator
    with MasksTestSettings {
  override lazy val width = 117
-  override lazy val memMaskGran = Some(13)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(13)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -345,8 +345,8 @@ class Masks_IntegerMaskMultiple_160_20
    with HasSimpleDepthTestGenerator
    with MasksTestSettings {
  override lazy val width = 160
-  override lazy val memMaskGran = Some(20)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(20)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -359,8 +359,8 @@ class Masks_IntegerMaskMultiple_184_23
    with HasSimpleDepthTestGenerator
    with MasksTestSettings {
  override lazy val width = 184
-  override lazy val memMaskGran = Some(23)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(23)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
@@ -375,8 +375,8 @@ class Masks_NonIntegerMaskMultiple_32_3
    with HasSimpleDepthTestGenerator
    with MasksTestSettings {
  override lazy val width = 32
-  override lazy val memMaskGran = Some(3)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(3)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  (it should "be enabled when non-power of two masks are supported").is(pending)
  //~ compileExecuteAndTest(mem, lib, v, output)
--- a/src/test/scala/barstools/macros/MultiPort.scala
+++ b/src/test/scala/barstools/macros/MultiPort.scala
@@ -8,10 +8,10 @@ class SplitWidth_2rw extends MacroCompilerSpec with HasSRAMGenerator with HasSim

  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 64
-  override lazy val memMaskGran = Some(16)
+  override lazy val memMaskGran: Option[Int] = Some(16)
  override lazy val libWidth = 16

-  override def generateMemSRAM() = {
+  override def generateMemSRAM(): SRAMMacro = {
    SRAMMacro(
      name = mem_name,
      width = memWidth,
@@ -42,7 +42,7 @@ class SplitWidth_2rw extends MacroCompilerSpec with HasSRAMGenerator with HasSim
    )
  }

-  override def generateLibSRAM() = {
+  override def generateLibSRAM(): SRAMMacro = {
    SRAMMacro(
      name = lib_name,
      width = libWidth,
@@ -71,16 +71,20 @@ class SplitWidth_2rw extends MacroCompilerSpec with HasSRAMGenerator with HasSim
    )
  }

-  override def generateHeaderPorts() = {
-    generateReadWriteHeaderPort("portA", true, Some(memMaskBits)) + "\n" + generateReadWriteHeaderPort(
+  override def generateHeaderPorts(): String = {
+    generateReadWriteHeaderPort("portA", readEnable = true, Some(memMaskBits)) + "\n" + generateReadWriteHeaderPort(
      "portB",
-      true,
+      readEnable = true,
      Some(memMaskBits)
    )
  }

-  override def generateFooterPorts() = {
-    generateReadWriteFooterPort("portA", true, None) + "\n" + generateReadWriteFooterPort("portB", true, None)
+  override def generateFooterPorts(): String = {
+    generateReadWriteFooterPort("portA", readEnable = true, None) + "\n" + generateReadWriteFooterPort(
+      "portB",
+      readEnable = true,
+      None
+    )
  }

  override def generateBody() =
@@ -151,10 +155,10 @@ class SplitWidth_1r_1w extends MacroCompilerSpec with HasSRAMGenerator with HasS

  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 64
-  override lazy val memMaskGran = Some(16)
+  override lazy val memMaskGran: Option[Int] = Some(16)
  override lazy val libWidth = 16

-  override def generateMemSRAM() = {
+  override def generateMemSRAM(): SRAMMacro = {
    SRAMMacro(
      name = mem_name,
      width = memWidth,
@@ -167,7 +171,6 @@ class SplitWidth_1r_1w extends MacroCompilerSpec with HasSRAMGenerator with HasS
          Some(memDepth),
          maskGran = memMaskGran,
          write = false,
-          writeEnable = false,
          read = true,
          readEnable = true
        ),
@@ -178,14 +181,13 @@ class SplitWidth_1r_1w extends MacroCompilerSpec with HasSRAMGenerator with HasS
          maskGran = memMaskGran,
          write = true,
          writeEnable = true,
-          read = false,
-          readEnable = false
+          read = false
        )
      )
    )
  }

-  override def generateLibSRAM() = {
+  override def generateLibSRAM(): SRAMMacro = {
    SRAMMacro(
      name = lib_name,
      width = libWidth,
@@ -197,24 +199,15 @@ class SplitWidth_1r_1w extends MacroCompilerSpec with HasSRAMGenerator with HasS
          libWidth,
          libDepth,
          write = false,
-          writeEnable = false,
          read = true,
          readEnable = true
        ),
-        generateTestPort(
-          "portB",
-          libWidth,
-          libDepth,
-          write = true,
-          writeEnable = true,
-          read = false,
-          readEnable = false
-        )
+        generateTestPort("portB", libWidth, libDepth, write = true, writeEnable = true, read = false)
      )
    )
  }

-  override def generateHeaderPorts() = {
+  override def generateHeaderPorts(): String = {
    generatePort(
      "portA",
      mem_addr_width,
@@ -237,7 +230,7 @@ class SplitWidth_1r_1w extends MacroCompilerSpec with HasSRAMGenerator with HasS
      )
  }

-  override def generateFooterPorts() = {
+  override def generateFooterPorts(): String = {
    generatePort(
      "portA",
      lib_addr_width,
@@ -310,12 +303,12 @@ class SplitWidth_2rw_differentMasks extends MacroCompilerSpec with HasSRAMGenera

  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 64
-  override lazy val memMaskGran = Some(16)
+  override lazy val memMaskGran: Option[Int] = Some(16)
  override lazy val libWidth = 16

  lazy val memMaskGranB = 8 // these generators are run at constructor time

-  override def generateMemSRAM() = {
+  override def generateMemSRAM(): SRAMMacro = {
    SRAMMacro(
      name = mem_name,
      width = memWidth,
@@ -346,7 +339,7 @@ class SplitWidth_2rw_differentMasks extends MacroCompilerSpec with HasSRAMGenera
    )
  }

-  override def generateLibSRAM() = {
+  override def generateLibSRAM(): SRAMMacro = {
    SRAMMacro(
      name = lib_name,
      width = libWidth,
@@ -375,16 +368,20 @@ class SplitWidth_2rw_differentMasks extends MacroCompilerSpec with HasSRAMGenera
    )
  }

-  override def generateHeaderPorts() = {
-    generateReadWriteHeaderPort("portA", true, Some(memMaskBits)) + "\n" + generateReadWriteHeaderPort(
+  override def generateHeaderPorts(): String = {
+    generateReadWriteHeaderPort("portA", readEnable = true, Some(memMaskBits)) + "\n" + generateReadWriteHeaderPort(
      "portB",
-      true,
+      readEnable = true,
      Some(memWidth / memMaskGranB)
    )
  }

-  override def generateFooterPorts() = {
-    generateReadWriteFooterPort("portA", true, None) + "\n" + generateReadWriteFooterPort("portB", true, None)
+  override def generateFooterPorts(): String = {
+    generateReadWriteFooterPort("portA", readEnable = true, None) + "\n" + generateReadWriteFooterPort(
+      "portB",
+      readEnable = true,
+      None
+    )
  }

  override def generateBody() =
--- a/src/test/scala/barstools/macros/SRAMCompiler.scala
+++ b/src/test/scala/barstools/macros/SRAMCompiler.scala
@@ -1,7 +1,9 @@
 package barstools.macros

+import mdf.macrolib
+
 class SRAMCompiler extends MacroCompilerSpec with HasSRAMGenerator with HasSimpleWidthTestGenerator {
-  val compiler = generateSRAMCompiler("awesome", "A")
+  val compiler: macrolib.SRAMCompiler = generateSRAMCompiler("awesome", "A")
  val verilog = s"v-SRAMCompiler.v"
  override lazy val depth = BigInt(16)
  override lazy val memWidth = 8
@@ -15,5 +17,5 @@ class SRAMCompiler extends MacroCompilerSpec with HasSRAMGenerator with HasSimpl

  writeToMem(mem, Seq(generateSRAM("mymem", "X", 8, 16)))

-  compileExecuteAndTest(mem, Some(lib), verilog, output = output, false, true)
+  compileExecuteAndTest(mem, Some(lib), verilog, output = output, useCompiler = true)
 }
--- a/src/test/scala/barstools/macros/SimpleSplitDepth.scala
+++ b/src/test/scala/barstools/macros/SimpleSplitDepth.scala
@@ -8,8 +8,8 @@ trait HasSimpleDepthTestGenerator extends HasSimpleTestGenerator {
  this: MacroCompilerSpec with HasSRAMGenerator =>
  def width: Int

-  override lazy val memWidth = width
-  override lazy val libWidth = width
+  override lazy val memWidth: Int = width
+  override lazy val libWidth: Int = width

  // Generate a depth-splitting body.
  override def generateBody(): String = {
@@ -19,37 +19,38 @@ trait HasSimpleDepthTestGenerator extends HasSimpleTestGenerator {
      output.append(
        s"""
    node ${memPortPrefix}_addr_sel = bits(${memPortPrefix}_addr, ${mem_addr_width - 1}, $lib_addr_width)
-    reg ${memPortPrefix}_addr_sel_reg : UInt<${selectBits}>, ${memPortPrefix}_clk with :
+    reg ${memPortPrefix}_addr_sel_reg : UInt<$selectBits>, ${memPortPrefix}_clk with :
      reset => (UInt<1>("h0"), ${memPortPrefix}_addr_sel_reg)
    ${memPortPrefix}_addr_sel_reg <= mux(UInt<1>("h1"), ${memPortPrefix}_addr_sel, ${memPortPrefix}_addr_sel_reg)
 """
      )
    }

-    for (i <- 0 to depthInstances - 1) {
+    for (i <- 0 until depthInstances) {
+
      val maskStatement = generateMaskStatement(0, i)
      val enableIdentifier =
-        if (selectBits > 0) s"""eq(${memPortPrefix}_addr_sel, UInt<${selectBits}>("h${i.toHexString}"))"""
+        if (selectBits > 0) s"""eq(${memPortPrefix}_addr_sel, UInt<$selectBits>("h${i.toHexString}"))"""
        else "UInt<1>(\"h1\")"
      val chipEnable = s"""UInt<1>("h1")"""
      val writeEnable =
-        if (memMaskGran.isEmpty) s"and(${memPortPrefix}_write_en, ${chipEnable})" else s"${memPortPrefix}_write_en"
+        if (memMaskGran.isEmpty) s"and(${memPortPrefix}_write_en, $chipEnable)" else s"${memPortPrefix}_write_en"
      output.append(
        s"""
-    inst mem_${i}_0 of ${lib_name}
+    inst mem_${i}_0 of $lib_name
    mem_${i}_0.${libPortPrefix}_clk <= ${memPortPrefix}_clk
    mem_${i}_0.${libPortPrefix}_addr <= ${memPortPrefix}_addr
    node ${memPortPrefix}_dout_${i}_0 = bits(mem_${i}_0.${libPortPrefix}_dout, ${width - 1}, 0)
    mem_${i}_0.${libPortPrefix}_din <= bits(${memPortPrefix}_din, ${width - 1}, 0)
-    ${maskStatement}
-    mem_${i}_0.${libPortPrefix}_write_en <= and(and(${writeEnable}, UInt<1>("h1")), ${enableIdentifier})
-    node ${memPortPrefix}_dout_${i} = ${memPortPrefix}_dout_${i}_0
+    $maskStatement
+    mem_${i}_0.${libPortPrefix}_write_en <= and(and($writeEnable, UInt<1>("h1")), $enableIdentifier)
+    node ${memPortPrefix}_dout_$i = ${memPortPrefix}_dout_${i}_0
  """
      )
    }
    def generate_outer_dout_tree(i: Int, depthInstances: Int): String = {
      if (i > depthInstances - 1) {
-        s"""UInt<${libWidth}>("h0")"""
+        s"""UInt<$libWidth>("h0")"""
      } else {
        s"""mux(eq(${memPortPrefix}_addr_sel_reg, UInt<%d>("h%s")), ${memPortPrefix}_dout_%d, %s)""".format(
          selectBits,
@@ -63,7 +64,7 @@ trait HasSimpleDepthTestGenerator extends HasSimpleTestGenerator {
    if (selectBits > 0) {
      output.append(generate_outer_dout_tree(0, depthInstances))
    } else {
-      output.append(s"""mux(UInt<1>("h1"), ${memPortPrefix}_dout_0, UInt<${libWidth}>("h0"))""")
+      output.append(s"""mux(UInt<1>("h1"), ${memPortPrefix}_dout_0, UInt<$libWidth>("h0"))""")
    }

    output.toString
@@ -143,8 +144,8 @@ class SplitDepth2048x32_mrw_lib32 extends MacroCompilerSpec with HasSRAMGenerato
  override lazy val width = 32
  override lazy val memDepth = BigInt(2048)
  override lazy val libDepth = BigInt(1024)
-  override lazy val memMaskGran = Some(32)
-  override lazy val libMaskGran = Some(32)
+  override lazy val memMaskGran: Option[Int] = Some(32)
+  override lazy val libMaskGran: Option[Int] = Some(32)

  compileExecuteAndTest(mem, lib, v, output)
 }
@@ -153,8 +154,8 @@ class SplitDepth2048x8_mrw_lib8 extends MacroCompilerSpec with HasSRAMGenerator
  override lazy val width = 8
  override lazy val memDepth = BigInt(2048)
  override lazy val libDepth = BigInt(1024)
-  override lazy val memMaskGran = Some(8)
-  override lazy val libMaskGran = Some(8)
+  override lazy val memMaskGran: Option[Int] = Some(8)
+  override lazy val libMaskGran: Option[Int] = Some(8)

  compileExecuteAndTest(mem, lib, v, output)
 }
@@ -167,8 +168,8 @@ class SplitDepth2048x64_mrw_mem32_lib8
  override lazy val width = 64
  override lazy val memDepth = BigInt(2048)
  override lazy val libDepth = BigInt(1024)
-  override lazy val memMaskGran = Some(32)
-  override lazy val libMaskGran = Some(8)
+  override lazy val memMaskGran: Option[Int] = Some(32)
+  override lazy val libMaskGran: Option[Int] = Some(8)

  compileExecuteAndTest(mem, lib, v, output)
 }
@@ -181,8 +182,8 @@ class SplitDepth2048x32_mrw_mem16_lib1
  override lazy val width = 32
  override lazy val memDepth = BigInt(2048)
  override lazy val libDepth = BigInt(1024)
-  override lazy val memMaskGran = Some(16)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(16)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  compileExecuteAndTest(mem, lib, v, output)
 }
@@ -191,8 +192,8 @@ class SplitDepth2048x32_mrw_mem8_lib1 extends MacroCompilerSpec with HasSRAMGene
  override lazy val width = 32
  override lazy val memDepth = BigInt(2048)
  override lazy val libDepth = BigInt(1024)
-  override lazy val memMaskGran = Some(8)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(8)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  compileExecuteAndTest(mem, lib, v, output)
 }
@@ -201,8 +202,8 @@ class SplitDepth2048x32_mrw_mem4_lib1 extends MacroCompilerSpec with HasSRAMGene
  override lazy val width = 32
  override lazy val memDepth = BigInt(2048)
  override lazy val libDepth = BigInt(1024)
-  override lazy val memMaskGran = Some(4)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(4)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  compileExecuteAndTest(mem, lib, v, output)
 }
@@ -211,8 +212,8 @@ class SplitDepth2048x32_mrw_mem2_lib1 extends MacroCompilerSpec with HasSRAMGene
  override lazy val width = 32
  override lazy val memDepth = BigInt(2048)
  override lazy val libDepth = BigInt(1024)
-  override lazy val memMaskGran = Some(2)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(2)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  compileExecuteAndTest(mem, lib, v, output)
 }
@@ -222,8 +223,8 @@ class SplitDepth2048x32_mrw_mem3_lib1 extends MacroCompilerSpec with HasSRAMGene
  override lazy val width = 32
  override lazy val memDepth = BigInt(2048)
  override lazy val libDepth = BigInt(1024)
-  override lazy val memMaskGran = Some(3)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(3)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  (it should "be enabled when non-power of two masks are supported").is(pending)
  //compileExecuteAndTest(mem, lib, v, output)
@@ -233,8 +234,8 @@ class SplitDepth2048x32_mrw_mem7_lib1 extends MacroCompilerSpec with HasSRAMGene
  override lazy val width = 32
  override lazy val memDepth = BigInt(2048)
  override lazy val libDepth = BigInt(1024)
-  override lazy val memMaskGran = Some(7)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(7)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  (it should "be enabled when non-power of two masks are supported").is(pending)
  //compileExecuteAndTest(mem, lib, v, output)
@@ -244,8 +245,8 @@ class SplitDepth2048x32_mrw_mem9_lib1 extends MacroCompilerSpec with HasSRAMGene
  override lazy val width = 32
  override lazy val memDepth = BigInt(2048)
  override lazy val libDepth = BigInt(1024)
-  override lazy val memMaskGran = Some(9)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(9)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  (it should "be enabled when non-power of two masks are supported").is(pending)
  //compileExecuteAndTest(mem, lib, v, output)
@@ -318,8 +319,8 @@ class SplitDepth_SplitPortsNonMasked extends MacroCompilerSpec with HasSRAMGener
  lazy val memDepth = BigInt(2048)
  lazy val libDepth = BigInt(1024)

-  override val memPrefix = testDir
-  override val libPrefix = testDir
+  override val memPrefix: String = testDir
+  override val libPrefix: String = testDir

  import mdf.macrolib._

@@ -476,11 +477,11 @@ class SplitDepth_SplitPortsMasked extends MacroCompilerSpec with HasSRAMGenerato
  lazy val width = 8
  lazy val memDepth = BigInt(2048)
  lazy val libDepth = BigInt(1024)
-  lazy val memMaskGran = Some(8)
-  lazy val libMaskGran = Some(1)
+  lazy val memMaskGran: Option[Int] = Some(8)
+  lazy val libMaskGran: Option[Int] = Some(1)

-  override val memPrefix = testDir
-  override val libPrefix = testDir
+  override val memPrefix: String = testDir
+  override val libPrefix: String = testDir

  import mdf.macrolib._

--- a/src/test/scala/barstools/macros/SimpleSplitWidth.scala
+++ b/src/test/scala/barstools/macros/SimpleSplitWidth.scala
@@ -7,23 +7,23 @@ trait HasSimpleWidthTestGenerator extends HasSimpleTestGenerator {
  this: MacroCompilerSpec with HasSRAMGenerator =>
  def depth: BigInt

-  override lazy val memDepth = depth
-  override lazy val libDepth = depth
+  override lazy val memDepth: BigInt = depth
+  override lazy val libDepth: BigInt = depth

  override def generateBody(): String = {
    val output = new StringBuilder

    // Generate mem_0_<i> lines for number of width instances.
    output.append(
-      ((0 to widthInstances - 1).map { i: Int =>
+      (0 until widthInstances).map { i: Int =>
        s"""
-    inst mem_0_${i} of ${lib_name}
+    inst mem_0_$i of $lib_name
 """
-      }).reduceLeft(_ + _)
+      }.reduceLeft(_ + _)
    )

    // Generate submemory connection blocks.
-    output.append((for (i <- 0 to widthInstances - 1) yield {
+    output.append((for (i <- 0 until widthInstances) yield {
      // Width of this submemory.
      val myMemWidth = if (i == widthInstances - 1) lastWidthBits else usableLibWidth
      // Base bit of this submemory.
@@ -37,34 +37,34 @@ trait HasSimpleWidthTestGenerator extends HasSimpleTestGenerator {
      // lib does not.
      val writeEnableBit = if (libMaskGran.isEmpty && memMaskGran.isDefined) {
        val outerMaskBit = myBaseBit / memMaskGran.get
-        s"bits(outer_mask, ${outerMaskBit}, ${outerMaskBit})"
+        s"bits(outer_mask, $outerMaskBit, $outerMaskBit)"
      } else """UInt<1>("h1")"""
      val chipEnable = s"""UInt<1>("h1")"""
      val writeEnableExpr =
-        if (libMaskGran.isEmpty) s"and(${memPortPrefix}_write_en, ${chipEnable})" else s"${memPortPrefix}_write_en"
+        if (libMaskGran.isEmpty) s"and(${memPortPrefix}_write_en, $chipEnable)" else s"${memPortPrefix}_write_en"

      s"""
-    mem_0_${i}.${libPortPrefix}_clk <= ${memPortPrefix}_clk
-    mem_0_${i}.${libPortPrefix}_addr <= ${memPortPrefix}_addr
-    node ${memPortPrefix}_dout_0_${i} = bits(mem_0_${i}.${libPortPrefix}_dout, ${myMemWidth - 1}, 0)
-    mem_0_${i}.${libPortPrefix}_din <= bits(${memPortPrefix}_din, ${myBaseBit + myMemWidth - 1}, ${myBaseBit})
-    ${maskStatement}
-    mem_0_${i}.${libPortPrefix}_write_en <= and(and(${writeEnableExpr}, ${writeEnableBit}), UInt<1>("h1"))
+    mem_0_$i.${libPortPrefix}_clk <= ${memPortPrefix}_clk
+    mem_0_$i.${libPortPrefix}_addr <= ${memPortPrefix}_addr
+    node ${memPortPrefix}_dout_0_$i = bits(mem_0_$i.${libPortPrefix}_dout, ${myMemWidth - 1}, 0)
+    mem_0_$i.${libPortPrefix}_din <= bits(${memPortPrefix}_din, ${myBaseBit + myMemWidth - 1}, $myBaseBit)
+    $maskStatement
+    mem_0_$i.${libPortPrefix}_write_en <= and(and($writeEnableExpr, $writeEnableBit), UInt<1>("h1"))
 """
    }).reduceLeft(_ + _))

    // Generate final output that concats together the sub-memories.
    // e.g. cat(outer_dout_0_2, cat(outer_dout_0_1, outer_dout_0_0))
    output.append {
-      val doutStatements = ((widthInstances - 1 to 0 by -1).map(i => s"${memPortPrefix}_dout_0_${i}"))
+      val doutStatements = (widthInstances - 1 to 0 by -1).map(i => s"${memPortPrefix}_dout_0_$i")
      val catStmt = doutStatements.init.foldRight(doutStatements.last)((l: String, r: String) => s"cat($l, $r)")
      s"""
-    node ${memPortPrefix}_dout_0 = ${catStmt}
+    node ${memPortPrefix}_dout_0 = $catStmt
 """
    }

    output.append(s"""
-    ${memPortPrefix}_dout <= mux(UInt<1>("h1"), ${memPortPrefix}_dout_0, UInt<${memWidth}>("h0"))
+    ${memPortPrefix}_dout <= mux(UInt<1>("h1"), ${memPortPrefix}_dout_0, UInt<$memWidth>("h0"))
 """)
    output.toString
  }
@@ -276,8 +276,8 @@ class SplitWidth1024x8_memGran_8_libGran_1_rw
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 8
  override lazy val libWidth = 8
-  override lazy val memMaskGran = Some(8)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(8)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  compileExecuteAndTest(mem, lib, v, output)
 }
@@ -289,8 +289,8 @@ class SplitWidth1024x16_memGran_8_libGran_1_rw
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 16
  override lazy val libWidth = 8
-  override lazy val memMaskGran = Some(8)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(8)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  compileExecuteAndTest(mem, lib, v, output)
 }
@@ -302,8 +302,8 @@ class SplitWidth1024x16_memGran_8_libGran_8_rw
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 16
  override lazy val libWidth = 8
-  override lazy val memMaskGran = Some(8)
-  override lazy val libMaskGran = Some(8)
+  override lazy val memMaskGran: Option[Int] = Some(8)
+  override lazy val libMaskGran: Option[Int] = Some(8)

  compileExecuteAndTest(mem, lib, v, output)
 }
@@ -315,8 +315,8 @@ class SplitWidth1024x128_memGran_8_libGran_1_rw
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 128
  override lazy val libWidth = 32
-  override lazy val memMaskGran = Some(8)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(8)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  compileExecuteAndTest(mem, lib, v, output)
 }
@@ -328,8 +328,8 @@ class SplitWidth1024x16_memGran_4_libGran_1_rw
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 16
  override lazy val libWidth = 8
-  override lazy val memMaskGran = Some(4)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(4)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  compileExecuteAndTest(mem, lib, v, output)
 }
@@ -341,8 +341,8 @@ class SplitWidth1024x16_memGran_2_libGran_1_rw
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 16
  override lazy val libWidth = 8
-  override lazy val memMaskGran = Some(2)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(2)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  compileExecuteAndTest(mem, lib, v, output)
 }
@@ -354,8 +354,8 @@ class SplitWidth1024x16_memGran_16_libGran_1_rw
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 16
  override lazy val libWidth = 8
-  override lazy val memMaskGran = Some(16)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(16)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  compileExecuteAndTest(mem, lib, v, output)
 }
@@ -366,7 +366,7 @@ class SplitWidth1024x16_libGran_8_rw extends MacroCompilerSpec with HasSRAMGener
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 16
  override lazy val libWidth = 8
-  override lazy val libMaskGran = Some(8)
+  override lazy val libMaskGran: Option[Int] = Some(8)

  compileExecuteAndTest(mem, lib, v, output)
 }
@@ -375,7 +375,7 @@ class SplitWidth1024x16_libGran_1_rw extends MacroCompilerSpec with HasSRAMGener
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 16
  override lazy val libWidth = 8
-  override lazy val libMaskGran = Some(1)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  compileExecuteAndTest(mem, lib, v, output)
 }
@@ -389,8 +389,8 @@ class SplitWidth1024x16_memGran_8_libGran_2_rw
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 16
  override lazy val libWidth = 8
-  override lazy val memMaskGran = Some(8)
-  override lazy val libMaskGran = Some(2)
+  override lazy val memMaskGran: Option[Int] = Some(8)
+  override lazy val libMaskGran: Option[Int] = Some(2)

  compileExecuteAndTest(mem, lib, v, output)
 }
@@ -404,8 +404,8 @@ class SplitWidth1024x16_memGran_9_libGran_1_rw
  override lazy val depth = BigInt(1024)
  override lazy val memWidth = 16
  override lazy val libWidth = 8
-  override lazy val memMaskGran = Some(9)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(9)
+  override lazy val libMaskGran: Option[Int] = Some(1)

  (it should "be enabled when non-power of two masks are supported").is(pending)
  //~ compile(mem, lib, v, false)
@@ -424,7 +424,7 @@ class SplitWidth1024x32_readEnable_Lib
  override lazy val memWidth = 32
  override lazy val libWidth = 8

-  override def generateLibSRAM() = {
+  override def generateLibSRAM(): SRAMMacro = {
    SRAMMacro(
      name = lib_name,
      width = libWidth,
@@ -492,7 +492,7 @@ class SplitWidth1024x32_readEnable_Mem
  override lazy val memWidth = 32
  override lazy val libWidth = 8

-  override def generateMemSRAM() = {
+  override def generateMemSRAM(): SRAMMacro = {
    SRAMMacro(
      name = mem_name,
      width = memWidth,
@@ -528,7 +528,7 @@ class SplitWidth1024x32_readEnable_LibMem
  override lazy val memWidth = 32
  override lazy val libWidth = 8

-  override def generateLibSRAM() = {
+  override def generateLibSRAM(): SRAMMacro = {
    SRAMMacro(
      name = lib_name,
      width = libWidth,
@@ -549,7 +549,7 @@ class SplitWidth1024x32_readEnable_LibMem
    )
  }

-  override def generateMemSRAM() = {
+  override def generateMemSRAM(): SRAMMacro = {
    SRAMMacro(
      name = mem_name,
      width = memWidth,
--- a/src/test/scala/barstools/macros/SpecificExamples.scala
+++ b/src/test/scala/barstools/macros/SpecificExamples.scala
@@ -1,7 +1,8 @@
 // See LICENSE for license details.
 package barstools.macros

-import mdf.macrolib._
+import firrtl.FileUtils
+import mdf.macrolib.{Constant, MacroExtraPort, SRAMMacro}

 // Specific one-off tests to run, not created by a generator.

@@ -17,7 +18,7 @@ class GenerateSomeVerilog extends MacroCompilerSpec with HasSRAMGenerator with H
  }

  it should "generate non-empty verilog" in {
-    val verilog = scala.io.Source.fromFile(vPrefix + "/" + v).getLines().mkString("\n")
+    val verilog = FileUtils.getText(vPrefix + "/" + v)
    verilog.isEmpty shouldBe false
  }
 }
@@ -29,7 +30,7 @@ class WriteEnableTest extends MacroCompilerSpec with HasSRAMGenerator {

  override val libPrefix = "src/test/resources"

-  val memSRAMs = mdf.macrolib.Utils
+  val memSRAMs: Seq[mdf.macrolib.Macro] = mdf.macrolib.Utils
    .readMDFFromString("""
 [ {
  "type" : "sram",
@@ -53,7 +54,7 @@ class WriteEnableTest extends MacroCompilerSpec with HasSRAMGenerator {
  } ],
  "family" : "1rw"
 } ]
-""").getOrElse(List())
+""").getOrElse(Seq())

  writeToMem(mem, memSRAMs)

@@ -101,7 +102,7 @@ class MaskPortTest extends MacroCompilerSpec with HasSRAMGenerator {

  override val libPrefix = "src/test/resources"

-  val memSRAMs = mdf.macrolib.Utils
+  val memSRAMs: Seq[mdf.macrolib.Macro] = mdf.macrolib.Utils
    .readMDFFromString("""
 [ {
  "type" : "sram",
@@ -175,7 +176,7 @@ circuit cc_dir_ext :
    defname = fake_mem
 """

-  it should "compile, exectue, and test" in {
+  it should "compile, execute, and test" in {
    compileExecuteAndTest(mem, lib, v, output)
  }
 }
@@ -187,7 +188,7 @@ class BOOMTest extends MacroCompilerSpec with HasSRAMGenerator {

  override val libPrefix = "src/test/resources"

-  val memSRAMs = mdf.macrolib.Utils
+  val memSRAMs: Seq[mdf.macrolib.Macro] = mdf.macrolib.Utils
    .readMDFFromString("""
 [ {
  "type" : "sram",
@@ -1461,7 +1462,7 @@ class RocketChipTest extends MacroCompilerSpec with HasSRAMGenerator {
    )
  )

-  val memSRAMs = mdf.macrolib.Utils
+  val memSRAMs: Seq[mdf.macrolib.Macro] = mdf.macrolib.Utils
    .readMDFFromString("""
 [
  {
--- a/src/test/scala/barstools/macros/SynFlops.scala
+++ b/src/test/scala/barstools/macros/SynFlops.scala
@@ -4,27 +4,27 @@ package barstools.macros

 trait HasSynFlopsTestGenerator extends HasSimpleTestGenerator {
  this: MacroCompilerSpec with HasSRAMGenerator =>
-  def generateFlops: String = {
+  def generateFlops(): String = {
    s"""
-    inst mem_0_0 of split_${lib_name}
+    inst mem_0_0 of split_$lib_name
    mem_0_0.${libPortPrefix}_clk <= ${libPortPrefix}_clk
    mem_0_0.${libPortPrefix}_addr <= ${libPortPrefix}_addr
    node ${libPortPrefix}_dout_0_0 = bits(mem_0_0.${libPortPrefix}_dout, ${libWidth - 1}, 0)
    mem_0_0.${libPortPrefix}_din <= bits(${libPortPrefix}_din, ${libWidth - 1}, 0)
    mem_0_0.${libPortPrefix}_write_en <= and(and(and(${libPortPrefix}_write_en, UInt<1>("h1")), UInt<1>("h1")), UInt<1>("h1"))
    node ${libPortPrefix}_dout_0 = ${libPortPrefix}_dout_0_0
-    ${libPortPrefix}_dout <= mux(UInt<1>("h1"), ${libPortPrefix}_dout_0, UInt<${libWidth}>("h0"))
+    ${libPortPrefix}_dout <= mux(UInt<1>("h1"), ${libPortPrefix}_dout_0, UInt<$libWidth>("h0"))

-  module split_${lib_name} :
-    input ${libPortPrefix}_addr : UInt<${lib_addr_width}>
+  module split_$lib_name :
+    input ${libPortPrefix}_addr : UInt<$lib_addr_width>
    input ${libPortPrefix}_clk : Clock
-    input ${libPortPrefix}_din : UInt<${libWidth}>
-    output ${libPortPrefix}_dout : UInt<${libWidth}>
+    input ${libPortPrefix}_din : UInt<$libWidth>
+    output ${libPortPrefix}_dout : UInt<$libWidth>
    input ${libPortPrefix}_write_en : UInt<1>

    mem ram :
-      data-type => UInt<${libWidth}>
-      depth => ${libDepth}
+      data-type => UInt<$libWidth>
+      depth => $libDepth
      read-latency => 1
      write-latency => 1
      readwriter => RW_0
@@ -40,20 +40,24 @@ trait HasSynFlopsTestGenerator extends HasSimpleTestGenerator {
  }

  // If there is no lib, put the flops definition into the body.
-  abstract override def generateBody = {
-    if (this.isInstanceOf[HasNoLibTestGenerator]) generateFlops else super.generateBody
+  abstract override def generateBody(): String = {
+    if (this.isInstanceOf[HasNoLibTestGenerator]) {
+      generateFlops()
+    } else {
+      super.generateBody()
+    }
  }

  // If there is no lib, don't generate a footer, since the flops definition
  // will be in the body.
-  override def generateFooter = {
+  override def generateFooter(): String = {
    if (this.isInstanceOf[HasNoLibTestGenerator]) ""
    else
      s"""
-  module ${lib_name} :
-${generateFooterPorts}
+  module $lib_name :
+${generateFooterPorts()}

-${generateFlops}
+${generateFlops()}
 """
  }

@@ -67,7 +71,7 @@ class Synflops2048x8_noLib
  override lazy val memDepth = BigInt(2048)
  override lazy val memWidth = 8

-  compileExecuteAndTest(mem, None, v, output, true)
+  compileExecuteAndTest(mem, None, v, output, synflops = true)
 }

 class Synflops2048x16_noLib
@@ -78,7 +82,7 @@ class Synflops2048x16_noLib
  override lazy val memDepth = BigInt(2048)
  override lazy val memWidth = 16

-  compileExecuteAndTest(mem, None, v, output, true)
+  compileExecuteAndTest(mem, None, v, output, synflops = true)
 }

 class Synflops8192x16_noLib
@@ -89,7 +93,7 @@ class Synflops8192x16_noLib
  override lazy val memDepth = BigInt(8192)
  override lazy val memWidth = 16

-  compileExecuteAndTest(mem, None, v, output, true)
+  compileExecuteAndTest(mem, None, v, output, synflops = true)
 }

 class Synflops2048x16_depth_Lib
@@ -101,7 +105,7 @@ class Synflops2048x16_depth_Lib
  override lazy val libDepth = BigInt(1024)
  override lazy val width = 16

-  compileExecuteAndTest(mem, lib, v, output, true)
+  compileExecuteAndTest(mem, lib, v, output, synflops = true)
 }

 class Synflops2048x64_width_Lib
@@ -113,7 +117,7 @@ class Synflops2048x64_width_Lib
  override lazy val libWidth = 8
  override lazy val depth = BigInt(1024)

-  compileExecuteAndTest(mem, lib, v, output, true)
+  compileExecuteAndTest(mem, lib, v, output, synflops = true)
 }

 class Synflops_SplitPorts_Read_Write
@@ -127,7 +131,7 @@ class Synflops_SplitPorts_Read_Write
  override lazy val libDepth = BigInt(1024)
  override lazy val width = 8

-  override def generateLibSRAM = SRAMMacro(
+  override def generateLibSRAM(): SRAMMacro = SRAMMacro(
    name = lib_name,
    width = width,
    depth = libDepth,
@@ -138,7 +142,7 @@ class Synflops_SplitPorts_Read_Write
    )
  )

-  override def generateMemSRAM = SRAMMacro(
+  override def generateMemSRAM(): SRAMMacro = SRAMMacro(
    name = mem_name,
    width = width,
    depth = memDepth,
@@ -149,7 +153,7 @@ class Synflops_SplitPorts_Read_Write
    )
  )

-  override def generateHeader =
+  override def generateHeader() =
    """
 circuit target_memory :
  module target_memory :
@@ -162,7 +166,7 @@ circuit target_memory :
    input outerA_write_en : UInt<1>
 """

-  override def generateBody =
+  override def generateBody() =
    """
    node outerB_addr_sel = bits(outerB_addr, 10, 10)
    reg outerB_addr_sel_reg : UInt<1>, outerB_clk with :
@@ -190,7 +194,7 @@ circuit target_memory :
    outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<8>("h0")))
 """

-  override def generateFooterPorts =
+  override def generateFooterPorts() =
    """
    input innerA_addr : UInt<10>
    input innerA_clk : Clock
@@ -201,7 +205,7 @@ circuit target_memory :
    input innerB_write_en : UInt<1>
 """

-  override def generateFlops =
+  override def generateFlops() =
    """
    inst mem_0_0 of split_awesome_lib_mem
    mem_0_0.innerB_clk <= innerB_clk
@@ -243,7 +247,7 @@ circuit target_memory :
 """

  "Non-masked split lib; split mem" should "syn flops fine" in {
-    compileExecuteAndTest(mem, lib, v, output, true)
+    compileExecuteAndTest(mem, lib, v, output, synflops = true)
  }
 }

@@ -257,10 +261,10 @@ class Synflops_SplitPorts_MaskedMem_Read_MaskedWrite
  override lazy val memDepth = BigInt(2048)
  override lazy val libDepth = BigInt(1024)
  override lazy val width = 8
-  override lazy val memMaskGran = Some(8)
-  override lazy val libMaskGran = Some(1)
+  override lazy val memMaskGran: Option[Int] = Some(8)
+  override lazy val libMaskGran: Option[Int] = Some(1)

-  override def generateLibSRAM = SRAMMacro(
+  override def generateLibSRAM(): SRAMMacro = SRAMMacro(
    name = lib_name,
    width = width,
    depth = libDepth,
@@ -271,7 +275,7 @@ class Synflops_SplitPorts_MaskedMem_Read_MaskedWrite
    )
  )

-  override def generateMemSRAM = SRAMMacro(
+  override def generateMemSRAM(): SRAMMacro = SRAMMacro(
    name = mem_name,
    width = width,
    depth = memDepth,
@@ -282,7 +286,7 @@ class Synflops_SplitPorts_MaskedMem_Read_MaskedWrite
    )
  )

-  override def generateHeader =
+  override def generateHeader() =
    """
 circuit target_memory :
  module target_memory :
@@ -296,7 +300,7 @@ circuit target_memory :
    input outerA_mask : UInt<1>
 """

-  override def generateBody =
+  override def generateBody() =
    """
    node outerB_addr_sel = bits(outerB_addr, 10, 10)
    reg outerB_addr_sel_reg : UInt<1>, outerB_clk with :
@@ -326,7 +330,7 @@ circuit target_memory :
    outerB_dout <= mux(eq(outerB_addr_sel_reg, UInt<1>("h0")), outerB_dout_0, mux(eq(outerB_addr_sel_reg, UInt<1>("h1")), outerB_dout_1, UInt<8>("h0")))
 """

-  override def generateFooterPorts =
+  override def generateFooterPorts() =
    """
    input innerA_addr : UInt<10>
    input innerA_clk : Clock
@@ -338,7 +342,7 @@ circuit target_memory :
    input innerB_mask : UInt<8>
 """

-  override def generateFlops =
+  override def generateFlops() =
    """
    inst mem_0_0 of split_awesome_lib_mem
    inst mem_0_1 of split_awesome_lib_mem
@@ -446,6 +450,6 @@ circuit target_memory :
 """

  "masked split lib; masked split mem" should "syn flops fine" in {
-    compileExecuteAndTest(mem, lib, v, output, true)
+    compileExecuteAndTest(mem, lib, v, output, synflops = true)
  }
 }
--- a/src/test/scala/barstools/tapeout/transforms/GenerateSpec.scala
+++ b/src/test/scala/barstools/tapeout/transforms/GenerateSpec.scala
@@ -17,7 +17,7 @@ class BlackBoxInverter extends ExtModule {
  val out = IO(Output(Bool()))
 }

-class GenerateExampleModule extends MultiIOModule {
+class GenerateExampleModule extends Module {
  val in = IO(Input(Bool()))
  val out = IO(Output(Bool()))

@@ -30,7 +30,7 @@ class GenerateExampleModule extends MultiIOModule {
  out := reg
 }

-class ToBeMadeExternal extends MultiIOModule {
+class ToBeMadeExternal extends Module {
  val in = IO(Input(Bool()))
  val out = IO(Output(Bool()))

@@ -39,7 +39,7 @@ class ToBeMadeExternal extends MultiIOModule {
  out := reg
 }

-class GenerateExampleTester extends MultiIOModule {
+class GenerateExampleTester extends Module {
  val success = IO(Output(Bool()))

  val mod = Module(new GenerateExampleModule)