diff --git a/.circleci/config.yml b/.circleci/config.yml index 5eda3c15..61b62e17 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -119,7 +119,7 @@ jobs: - run: name: Building the example subproject using Verilator - command: .circleci/do-rtl-build.sh example + command: .circleci/do-rtl-build.sh SUB_PROJECT=example no_output_timeout: 120m - save_cache: @@ -153,7 +153,7 @@ jobs: - run: name: Building the boomexample subproject using Verilator - command: .circleci/do-rtl-build.sh boomexample example SmallDefaultBoomConfig + command: .circleci/do-rtl-build.sh SUB_PROJECT=boomexample CONFIG=SmallDefaultBoomConfig no_output_timeout: 120m - save_cache: @@ -187,7 +187,7 @@ jobs: - run: name: Building the boom subproject using Verilator - command: .circleci/do-rtl-build.sh boom + command: .circleci/do-rtl-build.sh SUB_PROJECT=boom no_output_timeout: 120m - save_cache: @@ -221,7 +221,7 @@ jobs: - run: name: Building the rocketchip subproject using Verilator - command: .circleci/do-rtl-build.sh rocketchip + command: .circleci/do-rtl-build.sh SUB_PROJECT=rocketchip no_output_timeout: 120m - save_cache: @@ -255,7 +255,7 @@ jobs: - run: name: Building the hwacha subproject using Verilator - command: .circleci/do-rtl-build.sh hwacha example SmallHwachaConfig + command: .circleci/do-rtl-build.sh SUB_PROJECT=example MODEL=TestHarness MODEL_PACKAGE=freechips.rocketchip.system CONFIG=SmallHwachaConfig CONFIG_PACKAGE=example GENERATOR_PACKAGE=hwacha TOP=ExampleRocketSystem no_output_timeout: 120m - save_cache: @@ -401,7 +401,7 @@ jobs: - run: name: Run hwacha benchmark tests - command: make run-bmark-tests -C sims/verisim SUB_PROJECT=hwacha CONFIG_PACKAGE=example CONFIG=SmallHwachaConfig + command: make run-bmark-tests -C sims/verisim SUB_PROJECT=example MODEL=TestHarness MODEL_PACKAGE=freechips.rocketchip.system CONFIG=SmallHwachaConfig CONFIG_PACKAGE=example GENERATOR_PACKAGE=hwacha TOP=ExampleRocketSystem # Order and dependencies of jobs to run workflows: diff --git a/.circleci/do-rtl-build.sh b/.circleci/do-rtl-build.sh index eabce7c1..51ad760b 100755 --- a/.circleci/do-rtl-build.sh +++ b/.circleci/do-rtl-build.sh @@ -1,9 +1,7 @@ #!/bin/bash # create the different verilator builds -# 1st argument is the subproject -# 2nd argument is the config package (can be unspecified) -# 3nd argument is the config (can be unspecified) +# argument is the make command string # turn echo on and error on earliest command set -ex @@ -17,16 +15,6 @@ cd sims/verisim make clean # run the particular build command -if [ $# -ne 0 ]; then - if [ $# -eq 1 ]; then - make SUB_PROJECT=$1 JAVA_ARGS="-Xmx2G -Xss8M" - elif [ $# -eq 3 ]; then - make SUB_PROJECT=$1 CONFIG_PACKAGE=$2 CONFIG=$3 JAVA_ARGS="-Xmx2G -Xss8M" - else - exit 1 # wrong amount of args - fi -else - exit 1 # need to provide at least the arg -fi +make JAVA_ARGS="-Xmx2G -Xss8M" $@ rm -rf ../../project diff --git a/generators/example/src/main/scala/Configs.scala b/generators/example/src/main/scala/Configs.scala index 90b6cf89..aa9e6e3f 100644 --- a/generators/example/src/main/scala/Configs.scala +++ b/generators/example/src/main/scala/Configs.scala @@ -2,7 +2,7 @@ package example import chisel3._ import freechips.rocketchip.config.{Config} -import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize} +import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize, WithNBanks} import testchipip._ // -------------- @@ -22,9 +22,9 @@ class HwachaConfig extends Config( new DefaultRocketConfig) class SmallHwachaConfig extends Config( - new hwacha.WithNBanks(1) ++ + new WithNBanks(1) ++ new hwacha.DefaultHwachaConfig ++ - new DefaultConfig) + new freechips.rocketchip.system.DefaultConfig) class RoccRocketConfig extends Config( new WithRoccExample ++