From 7694695912654bffb8c845db9db881642405cc0f Mon Sep 17 00:00:00 2001 From: nayiri-k Date: Tue, 27 Sep 2022 12:29:57 -0700 Subject: [PATCH 1/4] updating docs --- docs/VLSI/Sky130-OpenROAD-Tutorial.rst | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst index 059412da..5b0c3fb0 100644 --- a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst +++ b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst @@ -34,10 +34,9 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo * All of the elaborated Chisel and FIRRTL. -* ``hammer``, ``hammer--plugins``, ``hammer--plugin`` +* ``hammer``, ``hammer/src/hammer-vlsi//``, ``hammer/src/hammer-vlsi/technology/`` - * Core repository, and commercial tool and NDA technology plugins. - * Open-source plugins are located under ``hammer/src/hammer-vlsi//`` and ``hammer/src/hammer-vlsi/technology/`` + * Core repository, and open-source tool and technology plugins. Prerequisites ------------- @@ -75,6 +74,15 @@ Pull the Hammer environment into the shell: Running the VLSI Flow --------------------- +For this tutorial we will be setting the Make variable ``tutorial=sky130-openroad`` to abbreviate the configuration. +The current options for this variable are defined in ``tutorial.mk``, a few of which are summarized as follows: + +* ``CONFIG=TinyRocketConfig`` selects the ``TinyRocketConfig`` from the Chipyard configurations. +* ``tech_name`` sets a few more necessary paths in the ``Makefile``, such as the appropriate Hammer plugin +* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-openroad.yml`` and ``example-sky130.yml``, which are described below +* ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml`` +* ``VLSI_OBJ_DIR`` gives the build directory a unique name to allow running multiple flows in the same repo. + example-vlsi-sky130 ^^^^^^^^^^^^^^^^^^^ This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. @@ -102,7 +110,7 @@ To map the generic memory macros in the generarted Verilog to the SRAMs in your .. code-block:: shell - make srams tech_name=sky130 CONFIG=TinyRocketConfig + make srams tutorial=sky130-openroad Generating Verilog ^^^^^^^^^^^^^^^^^^ @@ -110,7 +118,7 @@ To elaborate the ``TinyRocketConfig`` from Chisel to Verilog, run: .. code-block:: shell - make verilog tech_name=sky130 CONFIG=TinyRocketConfig + make verilog tutorial=sky130-openroad The ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime. The resulting verilog is located in ``./generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.v``. @@ -135,7 +143,7 @@ Synthesis .. code-block:: shell - make syn tech_name=sky130 CONFIG=TinyRocketConfig + make syn tutorial=sky130-openroad Post-synthesis logs and collateral are in ``build/syn-rundir``. @@ -145,7 +153,7 @@ Place-and-Route ^^^^^^^^^^^^^^^ .. code-block:: shell - make par tech_name=sky130 CONFIG=TinyRocketConfig + make par tutorial=sky130-openroad After completion, the final database can be opened in an interactive OpenROAD session. @@ -174,8 +182,8 @@ To run DRC & LVS: .. code-block:: shell - make drc tech_name=sky130 CONFIG=TinyRocketConfig - make lvs tech_name=sky130 CONFIG=TinyRocketConfig + make drc tutorial=sky130-openroad + make lvs tutorial=sky130-openroad Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the `Sky130 Hammer plugin README `__. From 49479754d3b101103635c764373d821a38213f2f Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 27 Sep 2022 14:04:54 -0700 Subject: [PATCH 2/4] minor tweaks --- vlsi/Makefile | 2 +- .../sky130-openroad-sramdev.yml | 51 ------------------- vlsi/tutorial.mk | 12 ----- 3 files changed, 1 insertion(+), 64 deletions(-) delete mode 100644 vlsi/example-designs/sky130-openroad-sramdev.yml diff --git a/vlsi/Makefile b/vlsi/Makefile index e73e22d4..d65bbbab 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -37,7 +37,7 @@ ENV_YML ?= $(vlsi_dir)/env.yml TECH_CONF ?= $(if $(filter $(tech_name),nangate45), example-nangate45.yml,\ $(if $(filter $(tech_name),asap7), example-asap7.yml,\ example-sky130.yml)) -TOOLS_CONF ?= example-tools.yml +TOOLS_CONF ?= example-tools.yml INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) HAMMER_EXEC ?= $(if $(filter $(tech_name),sky130),\ ./example-vlsi-sky130,\ diff --git a/vlsi/example-designs/sky130-openroad-sramdev.yml b/vlsi/example-designs/sky130-openroad-sramdev.yml deleted file mode 100644 index 8590a434..00000000 --- a/vlsi/example-designs/sky130-openroad-sramdev.yml +++ /dev/null @@ -1,51 +0,0 @@ -# Override configurations in ../example-sky130.yml - -# Specify clock signals -vlsi.inputs.clocks: [ - {name: "clock_clock", period: "10ns", uncertainty: "1ns"} -] - -# Power Straps -par.power_straps_mode: generate -par.generate_power_straps_method: by_tracks -par.blockage_spacing: 40.0 -par.blockage_spacing_top_layer: met4 -par.generate_power_straps_options: - by_tracks: - strap_layers: - - met4 - - met5 - pin_layers: - - met5 - blockage_spacing_met2: 4.0 - blockage_spacing_met4: 2.0 - blockage_spacing_met4: 2.0 - track_width: 3 - track_width_met5: 1 - track_spacing: 5 - track_start: 10 - track_start_met5: 1 - power_utilization: 0.1 - power_utilization_met4: 0.1 - power_utilization_met5: 0.1 - -# Placement Constraints -vlsi.inputs.placement_constraints: - - path: "ChipTop" - type: toplevel - x: 0 - y: 0 - width: 4000 - height: 2500 - margins: - left: 0 - right: 0 - top: 0 - bottom: 0 - -# Pin placement constraints -vlsi.inputs.pin_mode: generated -vlsi.inputs.pin.generate_mode: semi_auto -vlsi.inputs.pin.assignments: [ - {pins: "*", layers: ["met2", "met4"], side: "bottom"} -] diff --git a/vlsi/tutorial.mk b/vlsi/tutorial.mk index 023c7876..c85619e2 100644 --- a/vlsi/tutorial.mk +++ b/vlsi/tutorial.mk @@ -34,15 +34,3 @@ ifeq ($(tutorial),sky130-openroad) INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS) VLSI_OBJ_DIR ?= build-sky130-openroad endif - -ifeq ($(tutorial),sky130-openroad-sramdev) - tech_name ?= sky130 - CONFIG ?= TinyRocketConfig - TOOLS_CONF ?= example-openroad.yml - TECH_CONF ?= example-sky130.yml - DESIGN_CONF ?= example-designs/sky130-openroad-sramdev.yml - EXTRA_CONFS ?= $(if $(filter $(TOP),Rocket RocketTile), example-designs/sky130-rocket.yml, ) - INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS) - SMEMS_CACHE ?= $(abspath .)/hammer/src/hammer-vlsi/technology/sky130/sram-cache-dev.json - VLSI_OBJ_DIR ?= build-sky130-openroad-sramdev -endif \ No newline at end of file From be7bf0ed5be03186a294d7a23a04ecd497f7aa1f Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 27 Sep 2022 14:06:33 -0700 Subject: [PATCH 3/4] changed tabs to spaces in Makefile --- vlsi/Makefile | 226 +++++++++++++++++++++++++------------------------- 1 file changed, 113 insertions(+), 113 deletions(-) diff --git a/vlsi/Makefile b/vlsi/Makefile index d65bbbab..23b06813 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -28,15 +28,15 @@ SMEMS_CACHE ?= $(tech_dir)/sram-cache.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json ifdef USE_SRAM_COMPILER - MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict + MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict else - MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict -endif + MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict +endif ENV_YML ?= $(vlsi_dir)/env.yml -TECH_CONF ?= $(if $(filter $(tech_name),nangate45), example-nangate45.yml,\ - $(if $(filter $(tech_name),asap7), example-asap7.yml,\ - example-sky130.yml)) +TECH_CONF ?= $(if $(filter $(tech_name),nangate45), example-nangate45.yml,\ + $(if $(filter $(tech_name),asap7), example-asap7.yml,\ + example-sky130.yml)) TOOLS_CONF ?= example-tools.yml INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) HAMMER_EXEC ?= $(if $(filter $(tech_name),sky130),\ @@ -47,9 +47,9 @@ VLSI_HARNESS_DUT_NAME ?= chiptop # If overriding, this should be relative to $(vlsi_dir) VLSI_OBJ_DIR ?= build ifneq ($(CUSTOM_VLOG),) - OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/custom-$(VLSI_TOP) + OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/custom-$(VLSI_TOP) else - OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP) + OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP) endif ######################################################################################### @@ -58,11 +58,11 @@ endif ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE) extra_v_includes = $(build_dir)/EICG_wrapper.v ifneq ($(CUSTOM_VLOG), ) - VLSI_RTL = $(CUSTOM_VLOG) - VLSI_BB = /dev/null + VLSI_RTL = $(CUSTOM_VLOG) + VLSI_BB = /dev/null else - VLSI_RTL = $(ALL_RTL) $(extra_v_includes) - VLSI_BB = $(sim_top_blackboxes) + VLSI_RTL = $(ALL_RTL) $(extra_v_includes) + VLSI_BB = $(sim_top_blackboxes) endif .PHONY: default verilog @@ -92,13 +92,13 @@ sram_generator: $(SRAM_CONF) $(SMEMS_HAMMER): $(TOP_SMEMS_FILE) $(SRAM_GENERATOR_CONF): $(SMEMS_HAMMER) - mkdir -p $(dir $@) - echo "vlsi.inputs.sram_parameters: '$(SMEMS_HAMMER)'" >> $@ - echo "vlsi.inputs.sram_parameters_meta: [\"transclude\", \"json2list\"]">> $@ + mkdir -p $(dir $@) + echo "vlsi.inputs.sram_parameters: '$(SMEMS_HAMMER)'" >> $@ + echo "vlsi.inputs.sram_parameters_meta: [\"transclude\", \"json2list\"]">> $@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF) - cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator - cd $(vlsi_dir) && cp output.json $@ + cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator + cd $(vlsi_dir) && cp output.json $@ ######################################################################################### # simulation input configuration @@ -106,16 +106,16 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF) include $(base_dir)/vcs.mk SIM_FILE_REQS += \ - $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v + $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v # copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir) $(sim_files): $(SIM_FILE_REQS) | $(build_dir) - cp -f $^ $(build_dir) - $(foreach file,\ - $^,\ - $(if $(filter %.h,$(file)),\ - ,\ - echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;)) + cp -f $^ $(build_dir) + $(foreach file,\ + $^,\ + $(if $(filter %.h,$(file)),\ + ,\ + echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;)) SIM_CONF = $(OBJ_DIR)/sim-inputs.yml SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml @@ -123,97 +123,97 @@ SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml include $(vlsi_dir)/sim.mk $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) $(dramsim_lib) - mkdir -p $(dir $@) - echo "sim.inputs:" > $@ - echo " top_module: $(VLSI_TOP)" >> $@ - echo " input_files:" >> $@ - for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " input_files_meta: 'append'" >> $@ - echo " timescale: '1ns/10ps'" >> $@ - echo " options:" >> $@ - for x in $(VCS_NONCC_OPTS); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " options_meta: 'append'" >> $@ - echo " defines:" >> $@ - for x in $(subst +define+,,$(PREPROC_DEFINES)); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " defines_meta: 'append'" >> $@ - echo " compiler_cc_opts:" >> $@ - for x in $(filter-out "",$(VCS_CXXFLAGS)); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " compiler_cc_opts_meta: 'append'" >> $@ - echo " compiler_ld_opts:" >> $@ - for x in $(filter-out "",$(VCS_LDFLAGS)); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " compiler_ld_opts_meta: 'append'" >> $@ - echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ - echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ - echo " execution_flags:" >> $@ - for x in $(SIM_FLAGS); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " execution_flags_meta: 'append'" >> $@ + mkdir -p $(dir $@) + echo "sim.inputs:" > $@ + echo " top_module: $(VLSI_TOP)" >> $@ + echo " input_files:" >> $@ + for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " input_files_meta: 'append'" >> $@ + echo " timescale: '1ns/10ps'" >> $@ + echo " options:" >> $@ + for x in $(VCS_NONCC_OPTS); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " options_meta: 'append'" >> $@ + echo " defines:" >> $@ + for x in $(subst +define+,,$(PREPROC_DEFINES)); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " defines_meta: 'append'" >> $@ + echo " compiler_cc_opts:" >> $@ + for x in $(filter-out "",$(VCS_CXXFLAGS)); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " compiler_cc_opts_meta: 'append'" >> $@ + echo " compiler_ld_opts:" >> $@ + for x in $(filter-out "",$(VCS_LDFLAGS)); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " compiler_ld_opts_meta: 'append'" >> $@ + echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ + echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ + echo " execution_flags:" >> $@ + for x in $(SIM_FLAGS); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " execution_flags_meta: 'append'" >> $@ ifneq ($(BINARY), ) - echo " benchmarks: ['$(BINARY)']" >> $@ + echo " benchmarks: ['$(BINARY)']" >> $@ endif - echo " tb_dut: 'TestDriver.testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@ + echo " tb_dut: 'TestDriver.testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@ $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) - mkdir -p $(dir $@) - mkdir -p $(output_dir) - echo "sim.inputs:" > $@ - echo " defines: ['DEBUG']" >> $@ - echo " defines_meta: 'append'" >> $@ - echo " execution_flags:" >> $@ - for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " execution_flags_meta: 'append'" >> $@ - echo " saif.mode: 'time'" >> $@ - echo " saif.start_time: '0ns'" >> $@ - echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@ + mkdir -p $(dir $@) + mkdir -p $(output_dir) + echo "sim.inputs:" > $@ + echo " defines: ['DEBUG']" >> $@ + echo " defines_meta: 'append'" >> $@ + echo " execution_flags:" >> $@ + for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " execution_flags_meta: 'append'" >> $@ + echo " saif.mode: 'time'" >> $@ + echo " saif.start_time: '0ns'" >> $@ + echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@ ifdef USE_FSDB - echo " options:" >> $@ - echo ' - "-kdb"' >> $@ - echo " options_meta: 'append'" >> $@ - echo "sim.outputs.waveforms: ['$(sim_out_name).fsdb']" >> $@ + echo " options:" >> $@ + echo ' - "-kdb"' >> $@ + echo " options_meta: 'append'" >> $@ + echo "sim.outputs.waveforms: ['$(sim_out_name).fsdb']" >> $@ else - echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@ + echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@ endif $(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) - mkdir -p $(dir $@) - echo "sim.inputs:" > $@ - echo " defines: ['NTC']" >> $@ - echo " defines_meta: 'append'" >> $@ - echo " timing_annotated: 'true'" >> $@ + mkdir -p $(dir $@) + echo "sim.inputs:" > $@ + echo " defines: ['NTC']" >> $@ + echo " defines_meta: 'append'" >> $@ + echo " timing_annotated: 'true'" >> $@ POWER_CONF = $(OBJ_DIR)/power-inputs.yml include $(vlsi_dir)/power.mk $(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) - mkdir -p $(dir $@) - echo "power.inputs:" > $@ - echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@ - echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@ + mkdir -p $(dir $@) + echo "power.inputs:" > $@ + echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@ + echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@ ifneq ($(BINARY), ) - echo " waveforms: [" >> $@ + echo " waveforms: [" >> $@ ifdef USE_FSDB - echo " '$(sim_out_name).fsdb'" >> $@ + echo " '$(sim_out_name).fsdb'" >> $@ else - echo " '$(sim_out_name).vpd'" >> $@ + echo " '$(sim_out_name).vpd'" >> $@ endif - echo " ]" >> $@ + echo " ]" >> $@ endif - echo " start_times: ['0ns']" >> $@ - echo " end_times: [" >> $@ - echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@ - echo " ]" >> $@ + echo " start_times: ['0ns']" >> $@ + echo " end_times: [" >> $@ + echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@ + echo " ]" >> $@ ######################################################################################### # synthesis input configuration @@ -221,23 +221,23 @@ endif SYN_CONF = $(OBJ_DIR)/inputs.yml GENERATED_CONFS = $(SYN_CONF) ifeq ($(CUSTOM_VLOG), ) - GENERATED_CONFS += $(SRAM_CONF) + GENERATED_CONFS += $(SRAM_CONF) endif $(SYN_CONF): $(VLSI_RTL) $(VLSI_BB) - mkdir -p $(dir $@) - echo "sim.inputs:" > $@ - echo " input_files:" >> $@ - for x in $(VLSI_RTL); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " input_files_meta: 'append'" >> $@ - echo "synthesis.inputs:" >> $@ - echo " top_module: $(VLSI_TOP)" >> $@ - echo " input_files:" >> $@ - for x in $(VLSI_RTL) $(shell cat $(VLSI_BB)); do \ - echo ' - "'$$x'"' >> $@; \ - done + mkdir -p $(dir $@) + echo "sim.inputs:" > $@ + echo " input_files:" >> $@ + for x in $(VLSI_RTL); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " input_files_meta: 'append'" >> $@ + echo "synthesis.inputs:" >> $@ + echo " top_module: $(VLSI_TOP)" >> $@ + echo " input_files:" >> $@ + for x in $(VLSI_RTL) $(shell cat $(VLSI_BB)); do \ + echo ' - "'$$x'"' >> $@; \ + done ######################################################################################### # AUTO BUILD FLOW @@ -249,7 +249,7 @@ buildfile: $(OBJ_DIR)/hammer.d # TODO: make this dependency smarter so that we don't need this at all HAMMER_D_DEPS ?= $(GENERATED_CONFS) $(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS) - $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(GENERATED_CONFS), -p $(x)) --obj_dir $(OBJ_DIR) build + $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(GENERATED_CONFS), -p $(x)) --obj_dir $(OBJ_DIR) build -include $(OBJ_DIR)/hammer.d @@ -258,4 +258,4 @@ $(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS) ######################################################################################### .PHONY: clean clean: - rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF) + rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF) From 205895e45228b1611d4297f090f1f9cfb1377417 Mon Sep 17 00:00:00 2001 From: Nayiri K Date: Tue, 27 Sep 2022 14:12:53 -0700 Subject: [PATCH 4/4] undid some makefile changes --- docs/VLSI/Sky130-OpenROAD-Tutorial.rst | 26 ++- vlsi/Makefile | 226 ++++++++++++------------- 2 files changed, 130 insertions(+), 122 deletions(-) diff --git a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst index 059412da..5b0c3fb0 100644 --- a/docs/VLSI/Sky130-OpenROAD-Tutorial.rst +++ b/docs/VLSI/Sky130-OpenROAD-Tutorial.rst @@ -34,10 +34,9 @@ This example gives a suggested file structure and build system. The ``vlsi/`` fo * All of the elaborated Chisel and FIRRTL. -* ``hammer``, ``hammer--plugins``, ``hammer--plugin`` +* ``hammer``, ``hammer/src/hammer-vlsi//``, ``hammer/src/hammer-vlsi/technology/`` - * Core repository, and commercial tool and NDA technology plugins. - * Open-source plugins are located under ``hammer/src/hammer-vlsi//`` and ``hammer/src/hammer-vlsi/technology/`` + * Core repository, and open-source tool and technology plugins. Prerequisites ------------- @@ -75,6 +74,15 @@ Pull the Hammer environment into the shell: Running the VLSI Flow --------------------- +For this tutorial we will be setting the Make variable ``tutorial=sky130-openroad`` to abbreviate the configuration. +The current options for this variable are defined in ``tutorial.mk``, a few of which are summarized as follows: + +* ``CONFIG=TinyRocketConfig`` selects the ``TinyRocketConfig`` from the Chipyard configurations. +* ``tech_name`` sets a few more necessary paths in the ``Makefile``, such as the appropriate Hammer plugin +* ``TOOLS_CONF`` and ``TECH_CONF`` select the approproate YAML configuration files, ``example-openroad.yml`` and ``example-sky130.yml``, which are described below +* ``DESIGN_CONF`` and ``EXTRA_CONFS`` allow for additonal design-specific overrides of the Hammer IR in ``example-sky130.yml`` +* ``VLSI_OBJ_DIR`` gives the build directory a unique name to allow running multiple flows in the same repo. + example-vlsi-sky130 ^^^^^^^^^^^^^^^^^^^ This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. @@ -102,7 +110,7 @@ To map the generic memory macros in the generarted Verilog to the SRAMs in your .. code-block:: shell - make srams tech_name=sky130 CONFIG=TinyRocketConfig + make srams tutorial=sky130-openroad Generating Verilog ^^^^^^^^^^^^^^^^^^ @@ -110,7 +118,7 @@ To elaborate the ``TinyRocketConfig`` from Chisel to Verilog, run: .. code-block:: shell - make verilog tech_name=sky130 CONFIG=TinyRocketConfig + make verilog tutorial=sky130-openroad The ``CONFIG=TinyRocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a stripped-down Rocket Chip in the interest of minimizing tool runtime. The resulting verilog is located in ``./generated-src/chipyard.TestHarness.TinyRocketConfig/chipyard.TestHarness.TinyRocketConfig.top.v``. @@ -135,7 +143,7 @@ Synthesis .. code-block:: shell - make syn tech_name=sky130 CONFIG=TinyRocketConfig + make syn tutorial=sky130-openroad Post-synthesis logs and collateral are in ``build/syn-rundir``. @@ -145,7 +153,7 @@ Place-and-Route ^^^^^^^^^^^^^^^ .. code-block:: shell - make par tech_name=sky130 CONFIG=TinyRocketConfig + make par tutorial=sky130-openroad After completion, the final database can be opened in an interactive OpenROAD session. @@ -174,8 +182,8 @@ To run DRC & LVS: .. code-block:: shell - make drc tech_name=sky130 CONFIG=TinyRocketConfig - make lvs tech_name=sky130 CONFIG=TinyRocketConfig + make drc tutorial=sky130-openroad + make lvs tutorial=sky130-openroad Some DRC errors are expected from this PDK, especially with regards to the SRAMs, as explained in the `Sky130 Hammer plugin README `__. diff --git a/vlsi/Makefile b/vlsi/Makefile index 23b06813..2b64b74a 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -28,15 +28,15 @@ SMEMS_CACHE ?= $(tech_dir)/sram-cache.json SMEMS_HAMMER ?= $(build_dir)/$(long_name).mems.hammer.json ifdef USE_SRAM_COMPILER - MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict + MACROCOMPILER_MODE ?= -l $(SMEMS_COMP) --use-compiler -hir $(SMEMS_HAMMER) --mode strict else - MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict -endif + MACROCOMPILER_MODE ?= -l $(SMEMS_CACHE) -hir $(SMEMS_HAMMER) --mode strict +endif ENV_YML ?= $(vlsi_dir)/env.yml -TECH_CONF ?= $(if $(filter $(tech_name),nangate45), example-nangate45.yml,\ - $(if $(filter $(tech_name),asap7), example-asap7.yml,\ - example-sky130.yml)) +TECH_CONF ?= $(if $(filter $(tech_name),nangate45), example-nangate45.yml,\ + $(if $(filter $(tech_name),asap7), example-asap7.yml,\ + example-sky130.yml)) TOOLS_CONF ?= example-tools.yml INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) HAMMER_EXEC ?= $(if $(filter $(tech_name),sky130),\ @@ -47,9 +47,9 @@ VLSI_HARNESS_DUT_NAME ?= chiptop # If overriding, this should be relative to $(vlsi_dir) VLSI_OBJ_DIR ?= build ifneq ($(CUSTOM_VLOG),) - OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/custom-$(VLSI_TOP) + OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/custom-$(VLSI_TOP) else - OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP) + OBJ_DIR ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP) endif ######################################################################################### @@ -58,11 +58,11 @@ endif ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE) extra_v_includes = $(build_dir)/EICG_wrapper.v ifneq ($(CUSTOM_VLOG), ) - VLSI_RTL = $(CUSTOM_VLOG) - VLSI_BB = /dev/null + VLSI_RTL = $(CUSTOM_VLOG) + VLSI_BB = /dev/null else - VLSI_RTL = $(ALL_RTL) $(extra_v_includes) - VLSI_BB = $(sim_top_blackboxes) + VLSI_RTL = $(ALL_RTL) $(extra_v_includes) + VLSI_BB = $(sim_top_blackboxes) endif .PHONY: default verilog @@ -92,13 +92,13 @@ sram_generator: $(SRAM_CONF) $(SMEMS_HAMMER): $(TOP_SMEMS_FILE) $(SRAM_GENERATOR_CONF): $(SMEMS_HAMMER) - mkdir -p $(dir $@) - echo "vlsi.inputs.sram_parameters: '$(SMEMS_HAMMER)'" >> $@ - echo "vlsi.inputs.sram_parameters_meta: [\"transclude\", \"json2list\"]">> $@ + mkdir -p $(dir $@) + echo "vlsi.inputs.sram_parameters: '$(SMEMS_HAMMER)'" >> $@ + echo "vlsi.inputs.sram_parameters_meta: [\"transclude\", \"json2list\"]">> $@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF) - cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator - cd $(vlsi_dir) && cp output.json $@ + cd $(vlsi_dir) && $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(SRAM_GENERATOR_CONF), -p $(x)) --obj_dir $(build_dir) sram_generator + cd $(vlsi_dir) && cp output.json $@ ######################################################################################### # simulation input configuration @@ -106,16 +106,16 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF) include $(base_dir)/vcs.mk SIM_FILE_REQS += \ - $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v + $(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v # copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir) $(sim_files): $(SIM_FILE_REQS) | $(build_dir) - cp -f $^ $(build_dir) - $(foreach file,\ - $^,\ - $(if $(filter %.h,$(file)),\ - ,\ - echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;)) + cp -f $^ $(build_dir) + $(foreach file,\ + $^,\ + $(if $(filter %.h,$(file)),\ + ,\ + echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;)) SIM_CONF = $(OBJ_DIR)/sim-inputs.yml SIM_DEBUG_CONF = $(OBJ_DIR)/sim-debug-inputs.yml @@ -123,97 +123,97 @@ SIM_TIMING_CONF = $(OBJ_DIR)/sim-timing-inputs.yml include $(vlsi_dir)/sim.mk $(SIM_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) $(dramsim_lib) - mkdir -p $(dir $@) - echo "sim.inputs:" > $@ - echo " top_module: $(VLSI_TOP)" >> $@ - echo " input_files:" >> $@ - for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " input_files_meta: 'append'" >> $@ - echo " timescale: '1ns/10ps'" >> $@ - echo " options:" >> $@ - for x in $(VCS_NONCC_OPTS); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " options_meta: 'append'" >> $@ - echo " defines:" >> $@ - for x in $(subst +define+,,$(PREPROC_DEFINES)); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " defines_meta: 'append'" >> $@ - echo " compiler_cc_opts:" >> $@ - for x in $(filter-out "",$(VCS_CXXFLAGS)); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " compiler_cc_opts_meta: 'append'" >> $@ - echo " compiler_ld_opts:" >> $@ - for x in $(filter-out "",$(VCS_LDFLAGS)); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " compiler_ld_opts_meta: 'append'" >> $@ - echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ - echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ - echo " execution_flags:" >> $@ - for x in $(SIM_FLAGS); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " execution_flags_meta: 'append'" >> $@ + mkdir -p $(dir $@) + echo "sim.inputs:" > $@ + echo " top_module: $(VLSI_TOP)" >> $@ + echo " input_files:" >> $@ + for x in $(HARNESS_FILE) $(HARNESS_SMEMS_FILE); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " input_files_meta: 'append'" >> $@ + echo " timescale: '1ns/10ps'" >> $@ + echo " options:" >> $@ + for x in $(VCS_NONCC_OPTS); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " options_meta: 'append'" >> $@ + echo " defines:" >> $@ + for x in $(subst +define+,,$(PREPROC_DEFINES)); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " defines_meta: 'append'" >> $@ + echo " compiler_cc_opts:" >> $@ + for x in $(filter-out "",$(VCS_CXXFLAGS)); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " compiler_cc_opts_meta: 'append'" >> $@ + echo " compiler_ld_opts:" >> $@ + for x in $(filter-out "",$(VCS_LDFLAGS)); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " compiler_ld_opts_meta: 'append'" >> $@ + echo " execution_flags_prepend: ['$(PERMISSIVE_ON)']" >> $@ + echo " execution_flags_append: ['$(PERMISSIVE_OFF)']" >> $@ + echo " execution_flags:" >> $@ + for x in $(SIM_FLAGS); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " execution_flags_meta: 'append'" >> $@ ifneq ($(BINARY), ) - echo " benchmarks: ['$(BINARY)']" >> $@ + echo " benchmarks: ['$(BINARY)']" >> $@ endif - echo " tb_dut: 'TestDriver.testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@ + echo " tb_dut: 'TestDriver.testHarness.$(VLSI_HARNESS_DUT_NAME)'" >> $@ $(SIM_DEBUG_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) - mkdir -p $(dir $@) - mkdir -p $(output_dir) - echo "sim.inputs:" > $@ - echo " defines: ['DEBUG']" >> $@ - echo " defines_meta: 'append'" >> $@ - echo " execution_flags:" >> $@ - for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " execution_flags_meta: 'append'" >> $@ - echo " saif.mode: 'time'" >> $@ - echo " saif.start_time: '0ns'" >> $@ - echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@ + mkdir -p $(dir $@) + mkdir -p $(output_dir) + echo "sim.inputs:" > $@ + echo " defines: ['DEBUG']" >> $@ + echo " defines_meta: 'append'" >> $@ + echo " execution_flags:" >> $@ + for x in $(VERBOSE_FLAGS) $(WAVEFORM_FLAG); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " execution_flags_meta: 'append'" >> $@ + echo " saif.mode: 'time'" >> $@ + echo " saif.start_time: '0ns'" >> $@ + echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@ ifdef USE_FSDB - echo " options:" >> $@ - echo ' - "-kdb"' >> $@ - echo " options_meta: 'append'" >> $@ - echo "sim.outputs.waveforms: ['$(sim_out_name).fsdb']" >> $@ + echo " options:" >> $@ + echo ' - "-kdb"' >> $@ + echo " options_meta: 'append'" >> $@ + echo "sim.outputs.waveforms: ['$(sim_out_name).fsdb']" >> $@ else - echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@ + echo "sim.outputs.waveforms: ['$(sim_out_name).vpd']" >> $@ endif $(SIM_TIMING_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) - mkdir -p $(dir $@) - echo "sim.inputs:" > $@ - echo " defines: ['NTC']" >> $@ - echo " defines_meta: 'append'" >> $@ - echo " timing_annotated: 'true'" >> $@ + mkdir -p $(dir $@) + echo "sim.inputs:" > $@ + echo " defines: ['NTC']" >> $@ + echo " defines_meta: 'append'" >> $@ + echo " timing_annotated: 'true'" >> $@ POWER_CONF = $(OBJ_DIR)/power-inputs.yml include $(vlsi_dir)/power.mk $(POWER_CONF): $(VLSI_RTL) $(HARNESS_FILE) $(HARNESS_SMEMS_FILE) $(sim_common_files) - mkdir -p $(dir $@) - echo "power.inputs:" > $@ - echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@ - echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@ + mkdir -p $(dir $@) + echo "power.inputs:" > $@ + echo " tb_dut: 'testHarness/$(VLSI_HARNESS_DUT_NAME)'" >> $@ + echo " database: '$(OBJ_DIR)/par-rundir/$(VLSI_TOP)_FINAL'" >> $@ ifneq ($(BINARY), ) - echo " waveforms: [" >> $@ + echo " waveforms: [" >> $@ ifdef USE_FSDB - echo " '$(sim_out_name).fsdb'" >> $@ + echo " '$(sim_out_name).fsdb'" >> $@ else - echo " '$(sim_out_name).vpd'" >> $@ + echo " '$(sim_out_name).vpd'" >> $@ endif - echo " ]" >> $@ + echo " ]" >> $@ endif - echo " start_times: ['0ns']" >> $@ - echo " end_times: [" >> $@ - echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@ - echo " ]" >> $@ + echo " start_times: ['0ns']" >> $@ + echo " end_times: [" >> $@ + echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@ + echo " ]" >> $@ ######################################################################################### # synthesis input configuration @@ -221,23 +221,23 @@ endif SYN_CONF = $(OBJ_DIR)/inputs.yml GENERATED_CONFS = $(SYN_CONF) ifeq ($(CUSTOM_VLOG), ) - GENERATED_CONFS += $(SRAM_CONF) + GENERATED_CONFS += $(SRAM_CONF) endif $(SYN_CONF): $(VLSI_RTL) $(VLSI_BB) - mkdir -p $(dir $@) - echo "sim.inputs:" > $@ - echo " input_files:" >> $@ - for x in $(VLSI_RTL); do \ - echo ' - "'$$x'"' >> $@; \ - done - echo " input_files_meta: 'append'" >> $@ - echo "synthesis.inputs:" >> $@ - echo " top_module: $(VLSI_TOP)" >> $@ - echo " input_files:" >> $@ - for x in $(VLSI_RTL) $(shell cat $(VLSI_BB)); do \ - echo ' - "'$$x'"' >> $@; \ - done + mkdir -p $(dir $@) + echo "sim.inputs:" > $@ + echo " input_files:" >> $@ + for x in $(VLSI_RTL); do \ + echo ' - "'$$x'"' >> $@; \ + done + echo " input_files_meta: 'append'" >> $@ + echo "synthesis.inputs:" >> $@ + echo " top_module: $(VLSI_TOP)" >> $@ + echo " input_files:" >> $@ + for x in $(VLSI_RTL) $(shell cat $(VLSI_BB)); do \ + echo ' - "'$$x'"' >> $@; \ + done ######################################################################################### # AUTO BUILD FLOW @@ -249,7 +249,7 @@ buildfile: $(OBJ_DIR)/hammer.d # TODO: make this dependency smarter so that we don't need this at all HAMMER_D_DEPS ?= $(GENERATED_CONFS) $(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS) - $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(GENERATED_CONFS), -p $(x)) --obj_dir $(OBJ_DIR) build + $(HAMMER_EXEC) -e $(ENV_YML) $(foreach x,$(INPUT_CONFS) $(GENERATED_CONFS), -p $(x)) --obj_dir $(OBJ_DIR) build -include $(OBJ_DIR)/hammer.d @@ -258,4 +258,4 @@ $(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS) ######################################################################################### .PHONY: clean clean: - rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF) + rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF)