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Merge pull request #1060 from ucb-bar/chisel-3.5-published

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Bump to Chisel 3.5 RC
This commit is contained in:
Abraham Gonzalez
2022-02-10 17:09:06 -08:00
committed by GitHub
parent 534fde1c0f 40a5f36d50
commit 0fe908bfec
33 changed files with 82 additions and 108 deletions
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4
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -142,9 +142,9 @@ class LoopbackNICRocketConfig extends Config(
// DOC include start: l1scratchpadrocket
class ScratchpadOnlyRocketConfig extends Config(
new testchipip.WithSerialPBusMem ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port
new chipyard.config.WithL2TLBs(0) ++
new freechips.rocketchip.subsystem.WithNBanks(0) ++
new freechips.rocketchip.subsystem.WithNoMemPort ++
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port
new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 DCache scratchpad as base phys mem
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)

2
generators/chipyard/src/main/scala/example/InitZero.scala
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@@ -52,7 +52,7 @@ class InitZeroModuleImp(outer: InitZero) extends LazyModuleImp(outer) {
state := s_resp
}
when (mem.d.fire()) {
when (mem.d.fire) {
state := Mux(bytesLeft === 0.U, s_done, s_write)
}
}

2
generators/chipyard/src/main/scala/example/TutorialTile.scala
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@@ -28,6 +28,7 @@ case class MyCoreParams(
enableToFromHostCaching: Boolean = false,
) extends CoreParams {
val useVM: Boolean = true
val useHypervisor: Boolean = false
val useUser: Boolean = true
val useSupervisor: Boolean = false
val useDebug: Boolean = true
@@ -41,6 +42,7 @@ case class MyCoreParams(
val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket
val nLocalInterrupts: Int = 0
val useNMI: Boolean = false
val nPTECacheEntries: Int = 0 // TODO: Check
val nPMPs: Int = 0 // TODO: Check
val pmpGranularity: Int = 4 // copied from Rocket
val nBreakpoints: Int = 0 // TODO: Check

8
generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
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@@ -25,8 +25,6 @@ case object GenericFIRKey extends Field[Option[GenericFIRParams]](None)
class GenericFIRCellBundle[T<:Data:Ring](genIn:T, genOut:T) extends Bundle {
val data: T = genIn.cloneType
val carry: T = genOut.cloneType
override def cloneType: this.type = GenericFIRCellBundle(genIn, genOut).asInstanceOf[this.type]
}
object GenericFIRCellBundle {
def apply[T<:Data:Ring](genIn:T, genOut:T): GenericFIRCellBundle[T] = new GenericFIRCellBundle(genIn, genOut)
@@ -43,8 +41,6 @@ object GenericFIRCellIO {
class GenericFIRBundle[T<:Data:Ring](proto: T) extends Bundle {
val data: T = proto.cloneType
override def cloneType: this.type = GenericFIRBundle(proto).asInstanceOf[this.type]
}
object GenericFIRBundle {
def apply[T<:Data:Ring](proto: T): GenericFIRBundle[T] = new GenericFIRBundle(proto)
@@ -119,7 +115,7 @@ class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module {
// When a new transaction is ready on the input, we will have new data to output
// next cycle. Take this data in
when (io.in.fire()) {
when (io.in.fire) {
hasNewData := 1.U
inputReg := io.in.bits.data
}
@@ -127,7 +123,7 @@ class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module {
// We should output data when our cell has new data to output and is ready to
// recieve new data. This insures that every cell in the chain passes its data
// on at the same time
io.out.valid := hasNewData & io.in.fire()
io.out.valid := hasNewData & io.in.fire
io.out.bits.data := inputReg
// Compute carry

2
generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
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@@ -26,8 +26,6 @@ case object StreamingPassthroughKey extends Field[Option[StreamingPassthroughPar
class StreamingPassthroughBundle[T<:Data:Ring](proto: T) extends Bundle {
val data: T = proto.cloneType
override def cloneType: this.type = StreamingPassthroughBundle(proto).asInstanceOf[this.type]
}
object StreamingPassthroughBundle {
def apply[T<:Data:Ring](proto: T): StreamingPassthroughBundle[T] = new StreamingPassthroughBundle(proto)

3
generators/chipyard/src/main/scala/stage/ChipyardCli.scala
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@@ -10,6 +10,5 @@ trait ChipyardCli { this: Shell =>
parser.note("Chipyard Generator Options")
Seq(
UnderscoreDelimitedConfigsAnnotation
)
.foreach(_.addOptions(parser))
).foreach(_.addOptions(parser))
}

3
generators/chipyard/src/main/scala/stage/ChipyardStage.scala
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@@ -13,7 +13,7 @@ import freechips.rocketchip.system.RocketChipStage
import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain, Dependency}
import firrtl.options.phases.DeletedWrapper
class ChipyardStage extends ChiselStage with PreservesAll[Phase] {
class ChipyardStage extends ChiselStage {
override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli
override val targets: Seq[PhaseDependency] = Seq(
Dependency[freechips.rocketchip.stage.phases.Checks],
@@ -33,4 +33,5 @@ class ChipyardStage extends ChiselStage with PreservesAll[Phase] {
Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags],
Dependency[freechips.rocketchip.stage.phases.GenerateArtefacts],
)
override final def invalidates(a: Phase): Boolean = false
}

4
generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala
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@@ -22,7 +22,7 @@ import freechips.rocketchip.tile.XLen
import chipyard.TestSuiteHelper
import chipyard.TestSuitesKey
class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {
class AddDefaultTests extends Phase with HasRocketChipStageUtils {
// Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase
// because the RocketTestSuiteAnnotation is not serializable (but is not marked as such).
override val prerequisites = Seq(
@@ -52,4 +52,6 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS
implicit val p = getConfig(view[RocketChipOptions](annotations).configNames.get).toInstance
addTestSuiteAnnotations ++ oAnnos
}
override final def invalidates(a: Phase): Boolean = false
}

4
generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala
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@@ -21,7 +21,7 @@ trait MakefragSnippet { self: Annotation =>
case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotation with MakefragSnippet with Unserializable
/** Generates a make script to run tests in [[RocketTestSuiteAnnotation]]. */
class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {
class GenerateTestSuiteMakefrags extends Phase with HasRocketChipStageUtils {
// Our annotations tend not to be serializable, but are not marked as such.
override val prerequisites = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
@@ -46,4 +46,6 @@ class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with Has
writeOutputFile(targetDir, fileName, TestGeneration.generateMakeFrag ++ makefragBuilder.toString)
outputAnnotations
}
override final def invalidates(a: Phase): Boolean = false
}