Merge pull request #1060 from ucb-bar/chisel-3.5-published

Bump to Chisel 3.5 RC

generators/chipyard/src/main/scala/config/RocketConfigs.scala

@@ -142,9 +142,9 @@ class LoopbackNICRocketConfig extends Config(
 // DOC include start: l1scratchpadrocket
 class ScratchpadOnlyRocketConfig extends Config(
   new testchipip.WithSerialPBusMem ++
-  new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port
+  new chipyard.config.WithL2TLBs(0) ++
   new freechips.rocketchip.subsystem.WithNBanks(0) ++
-  new freechips.rocketchip.subsystem.WithNoMemPort ++
+  new freechips.rocketchip.subsystem.WithNoMemPort ++          // remove offchip mem port
   new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use rocket l1 DCache scratchpad as base phys mem
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new chipyard.config.AbstractConfig)

generators/chipyard/src/main/scala/example/InitZero.scala

@@ -52,7 +52,7 @@ class InitZeroModuleImp(outer: InitZero) extends LazyModuleImp(outer) {
     state := s_resp
   }
 
-  when (mem.d.fire()) {
+  when (mem.d.fire) {
     state := Mux(bytesLeft === 0.U, s_done, s_write)
   }
 }

generators/chipyard/src/main/scala/example/TutorialTile.scala

@@ -28,6 +28,7 @@ case class MyCoreParams(
   enableToFromHostCaching: Boolean = false,
 ) extends CoreParams {
   val useVM: Boolean = true
+  val useHypervisor: Boolean = false
   val useUser: Boolean = true
   val useSupervisor: Boolean = false
   val useDebug: Boolean = true
@@ -41,6 +42,7 @@ case class MyCoreParams(
   val fpu: Option[FPUParams] = Some(FPUParams()) // copied fma latencies from Rocket
   val nLocalInterrupts: Int = 0
   val useNMI: Boolean = false
+  val nPTECacheEntries: Int = 0 // TODO: Check
   val nPMPs: Int = 0 // TODO: Check
   val pmpGranularity: Int = 4 // copied from Rocket
   val nBreakpoints: Int = 0 // TODO: Check

generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala

@@ -25,8 +25,6 @@ case object GenericFIRKey extends Field[Option[GenericFIRParams]](None)
 class GenericFIRCellBundle[T<:Data:Ring](genIn:T, genOut:T) extends Bundle {
   val data: T = genIn.cloneType
   val carry: T = genOut.cloneType
-
-  override def cloneType: this.type = GenericFIRCellBundle(genIn, genOut).asInstanceOf[this.type]
 }
 object GenericFIRCellBundle {
   def apply[T<:Data:Ring](genIn:T, genOut:T): GenericFIRCellBundle[T] = new GenericFIRCellBundle(genIn, genOut)
@@ -43,8 +41,6 @@ object GenericFIRCellIO {
 
 class GenericFIRBundle[T<:Data:Ring](proto: T) extends Bundle {
   val data: T = proto.cloneType
-
-  override def cloneType: this.type = GenericFIRBundle(proto).asInstanceOf[this.type]
 }
 object GenericFIRBundle {
   def apply[T<:Data:Ring](proto: T): GenericFIRBundle[T] = new GenericFIRBundle(proto)
@@ -119,7 +115,7 @@ class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module {
 
   // When a new transaction is ready on the input, we will have new data to output
   // next cycle. Take this data in
-  when (io.in.fire()) {
+  when (io.in.fire) {
     hasNewData := 1.U
     inputReg := io.in.bits.data
   }
@@ -127,7 +123,7 @@ class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module {
   // We should output data when our cell has new data to output and is ready to
   // recieve new data. This insures that every cell in the chain passes its data
   // on at the same time
-  io.out.valid := hasNewData & io.in.fire()
+  io.out.valid := hasNewData & io.in.fire
   io.out.bits.data := inputReg
 
   // Compute carry

generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala

@@ -26,8 +26,6 @@ case object StreamingPassthroughKey extends Field[Option[StreamingPassthroughPar
 
 class StreamingPassthroughBundle[T<:Data:Ring](proto: T) extends Bundle {
     val data: T = proto.cloneType
-
-    override def cloneType: this.type = StreamingPassthroughBundle(proto).asInstanceOf[this.type]
 }
 object StreamingPassthroughBundle {
     def apply[T<:Data:Ring](proto: T): StreamingPassthroughBundle[T] = new StreamingPassthroughBundle(proto)

generators/chipyard/src/main/scala/stage/ChipyardCli.scala

@@ -10,6 +10,5 @@ trait ChipyardCli { this: Shell =>
   parser.note("Chipyard Generator Options")
   Seq(
     UnderscoreDelimitedConfigsAnnotation
-  )
-    .foreach(_.addOptions(parser))
+  ).foreach(_.addOptions(parser))
 }

generators/chipyard/src/main/scala/stage/ChipyardStage.scala

@@ -13,7 +13,7 @@ import freechips.rocketchip.system.RocketChipStage
 import firrtl.options.{Phase, PhaseManager, PreservesAll, Shell, Stage, StageError, StageMain, Dependency}
 import firrtl.options.phases.DeletedWrapper
 
-class ChipyardStage extends ChiselStage with PreservesAll[Phase] {
+class ChipyardStage extends ChiselStage {
   override val shell = new Shell("chipyard") with ChipyardCli with RocketChipCli with ChiselCli with FirrtlCli
   override val targets: Seq[PhaseDependency] = Seq(
     Dependency[freechips.rocketchip.stage.phases.Checks],
@@ -33,4 +33,5 @@ class ChipyardStage extends ChiselStage with PreservesAll[Phase] {
     Dependency[chipyard.stage.phases.GenerateTestSuiteMakefrags],
     Dependency[freechips.rocketchip.stage.phases.GenerateArtefacts],
   )
+  override final def invalidates(a: Phase): Boolean = false
 }

generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala

@@ -22,7 +22,7 @@ import freechips.rocketchip.tile.XLen
 import chipyard.TestSuiteHelper
 import chipyard.TestSuitesKey
 
-class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {
+class AddDefaultTests extends Phase with HasRocketChipStageUtils {
   // Make sure we run both after RocketChip's version of this phase, and Rocket Chip's annotation emission phase
   // because the RocketTestSuiteAnnotation is not serializable (but is not marked as such).
   override val prerequisites = Seq(
@@ -52,4 +52,6 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS
     implicit val p = getConfig(view[RocketChipOptions](annotations).configNames.get).toInstance
     addTestSuiteAnnotations ++ oAnnos
   }
+
+  override final def invalidates(a: Phase): Boolean = false
 }

generators/chipyard/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala

@@ -21,7 +21,7 @@ trait MakefragSnippet { self: Annotation =>
 case class CustomMakefragSnippet(val toMakefrag: String) extends NoTargetAnnotation with MakefragSnippet with Unserializable
 
 /** Generates a make script to run tests in [[RocketTestSuiteAnnotation]]. */
-class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with HasRocketChipStageUtils {
+class GenerateTestSuiteMakefrags extends Phase with HasRocketChipStageUtils {
 
   // Our annotations tend not to be serializable, but are not marked as such.
   override val prerequisites = Seq(Dependency[freechips.rocketchip.stage.phases.GenerateFirrtlAnnos],
@@ -46,4 +46,6 @@ class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with Has
     writeOutputFile(targetDir, fileName, TestGeneration.generateMakeFrag ++ makefragBuilder.toString)
     outputAnnotations
   }
+
+  override final def invalidates(a: Phase): Boolean = false
 }

generators/tracegen/src/main/scala/Tile.scala

@@ -66,10 +66,10 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
   tracegen_uop.ctrl.is_sta  := isWrite(io.tracegen.req.bits.cmd)
   tracegen_uop.ctrl.is_std  := isWrite(io.tracegen.req.bits.cmd)
 
-  io.lsu.dis_uops(0).valid         := io.tracegen.req.fire()
+  io.lsu.dis_uops(0).valid         := io.tracegen.req.fire
   io.lsu.dis_uops(0).bits          := tracegen_uop
 
-  when (io.tracegen.req.fire()) {
+  when (io.tracegen.req.fire) {
     rob_tail := WrapInc(rob_tail, rob_sz)
     rob_bsy(rob_tail)   := true.B
     rob_uop(rob_tail)   := tracegen_uop
@@ -111,7 +111,7 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
 
   assert(!io.lsu.lxcpt.valid)
 
-  io.lsu.exe(0).req.valid     := RegNext(io.tracegen.req.fire())
+  io.lsu.exe(0).req.valid     := RegNext(io.tracegen.req.fire)
   io.lsu.exe(0).req.bits      := DontCare
   io.lsu.exe(0).req.bits.uop  := RegNext(tracegen_uop)
   io.lsu.exe(0).req.bits.addr := RegNext(io.tracegen.req.bits.addr)
@@ -158,7 +158,7 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
 
   io.lsu.rob_head_idx := rob_head
 
-
+  io.tracegen.ordered := ready_for_amo && io.lsu.fencei_rdy
 }
 
 case class BoomTraceGenTileAttachParams(
@@ -236,6 +236,7 @@ class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile)
   ptw.io.requestors.head <> lsu.io.ptw
   outer.dcache.module.io.lsu <> lsu.io.dmem
   boom_shim.io.tracegen <> tracegen.io.mem
+  tracegen.io.fence_rdy := boom_shim.io.tracegen.ordered
   boom_shim.io.lsu <> lsu.io.core
 
   // Normally the PTW would use this port