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Merge pull request #1602 from ucb-bar/mihai-temp

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Updated docs on waveform generation to match current workflow.
This commit is contained in:
Jerry Zhao
2023-09-17 10:34:02 -07:00
committed by GitHub
parent 174ebc50b7 affbdc254b
commit 0fd04c302f
1 changed files with 2 additions and 2 deletions
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docs/Simulation/Software-RTL-Simulation.rst
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@@ -177,8 +177,8 @@ A special target that automatically generates the waveform file for a specific t
For a Verilator simulation, this will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer. For a Verilator simulation, this will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer.
An open-source vcd-capable waveform viewer is `GTKWave <http://gtkwave.sourceforge.net/>`__. An open-source vcd-capable waveform viewer is `GTKWave <http://gtkwave.sourceforge.net/>`__.
For a VCS simulation, this will generate a vpd file (this is a proprietary waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers. For a VCS simulation, this will generate an fsdb file that can be loaded to fsdb-supported waveform viewers.
If you have Synopsys licenses, we recommend using the DVE waveform viewer. If you have Synopsys licenses, we recommend using the Verdi waveform viewer.
Visualizing Chipyard SoCs Visualizing Chipyard SoCs
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