Unify configs between Chipyard and FireSim
This commit is contained in:
Jerry Zhao
@@ -14,7 +14,7 @@ import freechips.rocketchip.devices.tilelink.BootROMParams
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import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
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import freechips.rocketchip.diplomacy.LazyModule
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import boom.common.BoomTilesKey
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import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey}
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import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams}
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import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
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import scala.math.{min, max}
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import tracegen.TraceGenKey
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@@ -52,10 +52,6 @@ class WithPerfCounters extends Config((site, here, up) => {
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})
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class WithBoomEnableTrace extends Config((site, here, up) => {
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case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
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})
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// Disables clock-gating; doesn't play nice with our FAME-1 pass
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class WithoutClockGating extends Config((site, here, up) => {
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case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
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@@ -64,20 +60,37 @@ class WithoutClockGating extends Config((site, here, up) => {
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// Testing configurations
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// This enables printfs used in testing
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class WithScalaTestFeatures extends Config((site, here, up) => {
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case PrintTracePort => true
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case TracePortKey => up(TracePortKey, site).map(_.copy(print = true))
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})
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class WithFireSimTop extends Config((site, here, up) => {
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case BuildTop => (p: Parameters) => Module(LazyModule(new FireSimDUT()(p)).suggestName("top").module)
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})
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// FASED Config Aliases. This to enable config generation via "_" concatenation
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// which requires that all config classes be defined in the same package
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class DDR3FRFCFS extends FRFCFS16GBQuadRank
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class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB
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// L2 Config Aliases. For use with "_" concatenation
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class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache
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class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64)
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// Enables tracing on all cores
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class WithTraceIO extends Config((site, here, up) => {
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case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
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case TracePortKey => Some(TracePortParams())
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})
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// Tweaks that are generally applied to all firesim configs
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class WithFireSimConfigTweaks extends Config(
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new WithBootROM ++ // needed to support FireSim-as-top
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new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ // 3.2 GHz
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new WithoutClockGating ++
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new WithTraceIO ++
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new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++ // 16 GB
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new testchipip.WithTSI ++
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new testchipip.WithBlockDevice ++
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new chipyard.config.WithUART
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)
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/*******************************************************************************
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* Full TARGET_CONFIG configurations. These set parameters of the target being
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@@ -88,178 +101,69 @@ class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache
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* will store this name as part of the tags for the AGFI, so that later you can
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* reconstruct what is in a particular AGFI. These tags are also used to
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* determine which driver to build.
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*******************************************************************************/
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class FireSimRocketChipConfig extends Config(
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new chipyard.config.WithNoGPIO ++
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new WithBootROM ++
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new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
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new WithExtMemSize(0x400000000L) ++ // 16GB
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new WithoutTLMonitors ++
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new chipyard.config.WithUART ++
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new icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) ++
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new testchipip.WithTSI ++
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new testchipip.WithBlockDevice ++
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new chipyard.config.WithL2TLBs(1024) ++
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new WithPerfCounters ++
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new WithoutClockGating ++
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new WithDefaultMemModel ++
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*******************************************************************************/
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//*****************************************************************
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// Rocket configs, base off chipyard's RocketConfig
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//*****************************************************************
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class FireSimRocketConfig extends Config(
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new WithDefaultFireSimBridges ++
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new WithFireSimTop ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.system.DefaultConfig)
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class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => {
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case RocketTilesKey => List.tabulate(n)(i => up(RocketTilesKey).head.copy(hartId = i))
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})
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// single core config
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class FireSimRocketChipSingleCoreConfig extends Config(new FireSimRocketChipConfig)
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// dual core config
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class FireSimRocketChipDualCoreConfig extends Config(
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new WithNDuplicatedRocketCores(2) ++
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new FireSimRocketChipSingleCoreConfig)
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// quad core config
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class FireSimRocketChipQuadCoreConfig extends Config(
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new WithNDuplicatedRocketCores(4) ++
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new FireSimRocketChipSingleCoreConfig)
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// hexa core config
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class FireSimRocketChipHexaCoreConfig extends Config(
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new WithNDuplicatedRocketCores(6) ++
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new FireSimRocketChipSingleCoreConfig)
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// octa core config
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class FireSimRocketChipOctaCoreConfig extends Config(
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new WithNDuplicatedRocketCores(8) ++
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new FireSimRocketChipSingleCoreConfig)
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// SHA-3 accelerator config
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class FireSimRocketChipSha3L2Config extends Config(
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new WithInclusiveCache ++
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new sha3.WithSha3Accel ++
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new WithNBigCores(1) ++
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new FireSimRocketChipConfig)
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// SHA-3 accelerator config with synth printfs enabled
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class FireSimRocketChipSha3L2PrintfConfig extends Config(
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new WithInclusiveCache ++
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new sha3.WithSha3Printf ++
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new sha3.WithSha3Accel ++
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new WithNBigCores(1) ++
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new FireSimRocketChipConfig)
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class FireSimBoomConfig extends Config(
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new chipyard.config.WithNoGPIO ++
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new WithBootROM ++
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new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
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new WithExtMemSize(0x400000000L) ++ // 16GB
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new WithoutTLMonitors ++
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new WithBoomEnableTrace ++
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new chipyard.config.WithUART ++
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new icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) ++
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new testchipip.WithTSI ++
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new testchipip.WithBlockDevice ++
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new chipyard.config.WithL2TLBs(1024) ++
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new WithoutClockGating ++
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new WithDefaultMemModel ++
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new boom.common.WithLargeBooms ++
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new boom.common.WithNBoomCores(1) ++
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new WithFireSimConfigTweaks ++
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new chipyard.RocketConfig)
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class FireSimQuadRocketConfig extends Config(
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new WithDefaultFireSimBridges ++
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new WithFireSimTop ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.system.BaseConfig
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)
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new WithDefaultMemModel ++
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new WithFireSimConfigTweaks ++
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new chipyard.QuadRocketConfig)
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// A safer implementation than the one in BOOM in that it
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// duplicates whatever BOOMTileKey.head is present N times. This prevents
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// accidentally (and silently) blowing away configurations that may change the
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// tile in the "up" view
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class WithNDuplicatedBoomCores(n: Int) extends Config((site, here, up) => {
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case BoomTilesKey => List.tabulate(n)(i => up(BoomTilesKey).head.copy(hartId = i))
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case MaxHartIdBits => log2Up(site(BoomTilesKey).size)
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})
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class FireSimBoomDualCoreConfig extends Config(
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new WithNDuplicatedBoomCores(2) ++
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new FireSimBoomConfig)
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//*****************************************************************
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// Sha3 rocc-accel configs, base off chipyard's Sha3RocketConfig
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//*****************************************************************
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class FireSimSha3RocketConfig extends Config(
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new WithDefaultFireSimBridges ++
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new WithDefaultMemModel ++
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new WithFireSimConfigTweaks ++
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new chipyard.Sha3RocketConfig)
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class FireSimBoomQuadCoreConfig extends Config(
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new WithNDuplicatedBoomCores(4) ++
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new FireSimBoomConfig)
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class FireSimSha3PrintfRocketConfig extends Config(
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new sha3.WithSha3Printf ++
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new FireSimSha3RocketConfig)
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//*****************************************************************
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// Boom config, base off chipyard's LargeBoomConfig
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//*****************************************************************
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class FireSimLargeBoomConfig extends Config(
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new WithDefaultFireSimBridges ++
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new WithDefaultMemModel ++
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new WithFireSimConfigTweaks ++
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new chipyard.LargeBoomConfig)
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//********************************************************************
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// Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig
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//********************************************************************
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class FireSimLargeBoomAndRocketConfig extends Config(
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new WithDefaultFireSimBridges ++
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new WithDefaultMemModel ++
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new WithFireSimConfigTweaks ++
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new chipyard.LargeBoomAndRocketConfig)
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//******************************************************************
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// Gemmini NN accel config, base off chipyard's GemminiRocketConfig
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//******************************************************************
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class FireSimGemminiRocketConfig extends Config(
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new WithDefaultFireSimBridges ++
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new WithDefaultMemModel ++
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new WithFireSimConfigTweaks ++
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new chipyard.GemminiRocketConfig)
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//**********************************************************************************
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//* Heterogeneous Configurations
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//*********************************************************************************/
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// dual core config (rocket + small boom)
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class FireSimRocketBoomConfig extends Config(
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new chipyard.config.WithL2TLBs(1024) ++ // reset l2 tlb amt ("WithSmallBooms" overrides it)
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new boom.common.WithRenumberHarts ++ // fix hart numbering
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new boom.common.WithSmallBooms ++ // change single BOOM to small
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add a "big" rocket core
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new FireSimBoomConfig
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)
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// Supernode Configurations, base off chipyard's RocketConfig
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//**********************************************************************************
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//* Gemmini Configurations
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//*********************************************************************************/
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// Gemmini systolic accelerator default config
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class FireSimRocketChipGemminiL2Config extends Config(
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new WithInclusiveCache ++
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new gemmini.DefaultGemminiConfig ++
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new WithNBigCores(1) ++
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new FireSimRocketChipConfig)
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//**********************************************************************************
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//* Supernode Configurations
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//*********************************************************************************/
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class SupernodeFireSimRocketChipConfig extends Config(
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class SupernodeFireSimRocketConfig extends Config(
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new WithNumNodes(4) ++
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new WithExtMemSize(0x200000000L) ++ // 8GB
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new FireSimRocketChipConfig)
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class SupernodeFireSimRocketChipSingleCoreConfig extends Config(
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new WithNumNodes(4) ++
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new WithExtMemSize(0x200000000L) ++ // 8GB
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new FireSimRocketChipSingleCoreConfig)
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class SupernodeSixNodeFireSimRocketChipSingleCoreConfig extends Config(
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new WithNumNodes(6) ++
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new WithExtMemSize(0x40000000L) ++ // 1GB
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new FireSimRocketChipSingleCoreConfig)
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class SupernodeEightNodeFireSimRocketChipSingleCoreConfig extends Config(
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new WithNumNodes(8) ++
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new WithExtMemSize(0x40000000L) ++ // 1GB
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new FireSimRocketChipSingleCoreConfig)
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class SupernodeFireSimRocketChipDualCoreConfig extends Config(
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new WithNumNodes(4) ++
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new WithExtMemSize(0x200000000L) ++ // 8GB
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new FireSimRocketChipDualCoreConfig)
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class SupernodeFireSimRocketChipQuadCoreConfig extends Config(
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new WithNumNodes(4) ++
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new WithExtMemSize(0x200000000L) ++ // 8GB
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new FireSimRocketChipQuadCoreConfig)
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class SupernodeFireSimRocketChipHexaCoreConfig extends Config(
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new WithNumNodes(4) ++
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new WithExtMemSize(0x200000000L) ++ // 8GB
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new FireSimRocketChipHexaCoreConfig)
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class SupernodeFireSimRocketChipOctaCoreConfig extends Config(
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new WithNumNodes(4) ++
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new WithExtMemSize(0x200000000L) ++ // 8GB
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new FireSimRocketChipOctaCoreConfig)
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new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 8L) ++ // 8 GB
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new FireSimRocketConfig)
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