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Unify configs between Chipyard and FireSim

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This commit is contained in:
Jerry Zhao
2020-02-11 17:46:21 -08:00
parent ebfa545344
commit 0f56c4ce44
9 changed files with 91 additions and 283 deletions
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5
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -12,7 +12,7 @@ import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp}
import freechips.rocketchip.tile.{RocketTile}
import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp}
import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp, CanHaveTraceIOModuleImp}
import icenet.CanHavePeripheryIceNICModuleImp
import junctions.{NastiKey, NastiParameters}
@@ -59,7 +59,7 @@ class WithFASEDBridge extends RegisterIOBinder({
})
class WithTracerVBridge extends RegisterIOBinder({
(c, r, s, target: HasTraceIOImp) => Seq(TracerVBridge(target.traceIO)(target.p))
(c, r, s, target: CanHaveTraceIOModuleImp) => target.traceIO.map(t => TracerVBridge(t)(target.p)).toSeq
})
class WithTraceGenBridge extends RegisterIOBinder({
@@ -93,6 +93,7 @@ class WithFireSimMultiCycleRegfile extends RegisterIOBinder({
// Shorthand to register all of the provided bridges above
class WithDefaultFireSimBridges extends Config(
new chipyard.iobinders.WithGPIOTiedOff ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithTieOffInterrupts ++
new WithSerialBridge ++

256
generators/firechip/src/main/scala/TargetConfigs.scala
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@@ -14,7 +14,7 @@ import freechips.rocketchip.devices.tilelink.BootROMParams
import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
import freechips.rocketchip.diplomacy.LazyModule
import boom.common.BoomTilesKey
import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey}
import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import scala.math.{min, max}
import tracegen.TraceGenKey
@@ -52,10 +52,6 @@ class WithPerfCounters extends Config((site, here, up) => {
})
class WithBoomEnableTrace extends Config((site, here, up) => {
case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
})
// Disables clock-gating; doesn't play nice with our FAME-1 pass
class WithoutClockGating extends Config((site, here, up) => {
case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))
@@ -64,20 +60,37 @@ class WithoutClockGating extends Config((site, here, up) => {
// Testing configurations
// This enables printfs used in testing
class WithScalaTestFeatures extends Config((site, here, up) => {
case PrintTracePort => true
case TracePortKey => up(TracePortKey, site).map(_.copy(print = true))
})
class WithFireSimTop extends Config((site, here, up) => {
case BuildTop => (p: Parameters) => Module(LazyModule(new FireSimDUT()(p)).suggestName("top").module)
})
// FASED Config Aliases. This to enable config generation via "_" concatenation
// which requires that all config classes be defined in the same package
class DDR3FRFCFS extends FRFCFS16GBQuadRank
class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB
// L2 Config Aliases. For use with "_" concatenation
class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache
class WithNIC extends icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64)
// Enables tracing on all cores
class WithTraceIO extends Config((site, here, up) => {
case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
case TracePortKey => Some(TracePortParams())
})
// Tweaks that are generally applied to all firesim configs
class WithFireSimConfigTweaks extends Config(
new WithBootROM ++ // needed to support FireSim-as-top
new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ // 3.2 GHz
new WithoutClockGating ++
new WithTraceIO ++
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 16L) ++ // 16 GB
new testchipip.WithTSI ++
new testchipip.WithBlockDevice ++
new chipyard.config.WithUART
)
/*******************************************************************************
* Full TARGET_CONFIG configurations. These set parameters of the target being
@@ -88,178 +101,69 @@ class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache
* will store this name as part of the tags for the AGFI, so that later you can
* reconstruct what is in a particular AGFI. These tags are also used to
* determine which driver to build.
*******************************************************************************/
class FireSimRocketChipConfig extends Config(
new chipyard.config.WithNoGPIO ++
new WithBootROM ++
new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
new WithExtMemSize(0x400000000L) ++ // 16GB
new WithoutTLMonitors ++
new chipyard.config.WithUART ++
new icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) ++
new testchipip.WithTSI ++
new testchipip.WithBlockDevice ++
new chipyard.config.WithL2TLBs(1024) ++
new WithPerfCounters ++
new WithoutClockGating ++
new WithDefaultMemModel ++
*******************************************************************************/
//*****************************************************************
// Rocket configs, base off chipyard's RocketConfig
//*****************************************************************
class FireSimRocketConfig extends Config(
new WithDefaultFireSimBridges ++
new WithFireSimTop ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.system.DefaultConfig)
class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => {
case RocketTilesKey => List.tabulate(n)(i => up(RocketTilesKey).head.copy(hartId = i))
})
// single core config
class FireSimRocketChipSingleCoreConfig extends Config(new FireSimRocketChipConfig)
// dual core config
class FireSimRocketChipDualCoreConfig extends Config(
new WithNDuplicatedRocketCores(2) ++
new FireSimRocketChipSingleCoreConfig)
// quad core config
class FireSimRocketChipQuadCoreConfig extends Config(
new WithNDuplicatedRocketCores(4) ++
new FireSimRocketChipSingleCoreConfig)
// hexa core config
class FireSimRocketChipHexaCoreConfig extends Config(
new WithNDuplicatedRocketCores(6) ++
new FireSimRocketChipSingleCoreConfig)
// octa core config
class FireSimRocketChipOctaCoreConfig extends Config(
new WithNDuplicatedRocketCores(8) ++
new FireSimRocketChipSingleCoreConfig)
// SHA-3 accelerator config
class FireSimRocketChipSha3L2Config extends Config(
new WithInclusiveCache ++
new sha3.WithSha3Accel ++
new WithNBigCores(1) ++
new FireSimRocketChipConfig)
// SHA-3 accelerator config with synth printfs enabled
class FireSimRocketChipSha3L2PrintfConfig extends Config(
new WithInclusiveCache ++
new sha3.WithSha3Printf ++
new sha3.WithSha3Accel ++
new WithNBigCores(1) ++
new FireSimRocketChipConfig)
class FireSimBoomConfig extends Config(
new chipyard.config.WithNoGPIO ++
new WithBootROM ++
new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
new WithExtMemSize(0x400000000L) ++ // 16GB
new WithoutTLMonitors ++
new WithBoomEnableTrace ++
new chipyard.config.WithUART ++
new icenet.WithIceNIC(inBufFlits = 8192, ctrlQueueDepth = 64) ++
new testchipip.WithTSI ++
new testchipip.WithBlockDevice ++
new chipyard.config.WithL2TLBs(1024) ++
new WithoutClockGating ++
new WithDefaultMemModel ++
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(1) ++
new WithFireSimConfigTweaks ++
new chipyard.RocketConfig)
class FireSimQuadRocketConfig extends Config(
new WithDefaultFireSimBridges ++
new WithFireSimTop ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.system.BaseConfig
)
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new chipyard.QuadRocketConfig)
// A safer implementation than the one in BOOM in that it
// duplicates whatever BOOMTileKey.head is present N times. This prevents
// accidentally (and silently) blowing away configurations that may change the
// tile in the "up" view
class WithNDuplicatedBoomCores(n: Int) extends Config((site, here, up) => {
case BoomTilesKey => List.tabulate(n)(i => up(BoomTilesKey).head.copy(hartId = i))
case MaxHartIdBits => log2Up(site(BoomTilesKey).size)
})
class FireSimBoomDualCoreConfig extends Config(
new WithNDuplicatedBoomCores(2) ++
new FireSimBoomConfig)
//*****************************************************************
// Sha3 rocc-accel configs, base off chipyard's Sha3RocketConfig
//*****************************************************************
class FireSimSha3RocketConfig extends Config(
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new chipyard.Sha3RocketConfig)
class FireSimBoomQuadCoreConfig extends Config(
new WithNDuplicatedBoomCores(4) ++
new FireSimBoomConfig)
class FireSimSha3PrintfRocketConfig extends Config(
new sha3.WithSha3Printf ++
new FireSimSha3RocketConfig)
//*****************************************************************
// Boom config, base off chipyard's LargeBoomConfig
//*****************************************************************
class FireSimLargeBoomConfig extends Config(
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new chipyard.LargeBoomConfig)
//********************************************************************
// Heterogeneous config, base off chipyard's LargeBoomAndRocketConfig
//********************************************************************
class FireSimLargeBoomAndRocketConfig extends Config(
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new chipyard.LargeBoomAndRocketConfig)
//******************************************************************
// Gemmini NN accel config, base off chipyard's GemminiRocketConfig
//******************************************************************
class FireSimGemminiRocketConfig extends Config(
new WithDefaultFireSimBridges ++
new WithDefaultMemModel ++
new WithFireSimConfigTweaks ++
new chipyard.GemminiRocketConfig)
//**********************************************************************************
//* Heterogeneous Configurations
//*********************************************************************************/
// dual core config (rocket + small boom)
class FireSimRocketBoomConfig extends Config(
new chipyard.config.WithL2TLBs(1024) ++ // reset l2 tlb amt ("WithSmallBooms" overrides it)
new boom.common.WithRenumberHarts ++ // fix hart numbering
new boom.common.WithSmallBooms ++ // change single BOOM to small
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // add a "big" rocket core
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new FireSimBoomConfig
)
// Supernode Configurations, base off chipyard's RocketConfig
//**********************************************************************************
//* Gemmini Configurations
//*********************************************************************************/
// Gemmini systolic accelerator default config
class FireSimRocketChipGemminiL2Config extends Config(
new WithInclusiveCache ++
new gemmini.DefaultGemminiConfig ++
new WithNBigCores(1) ++
new FireSimRocketChipConfig)
//**********************************************************************************
//* Supernode Configurations
//*********************************************************************************/
class SupernodeFireSimRocketChipConfig extends Config(
class SupernodeFireSimRocketConfig extends Config(
new WithNumNodes(4) ++
new WithExtMemSize(0x200000000L) ++ // 8GB
new FireSimRocketChipConfig)
class SupernodeFireSimRocketChipSingleCoreConfig extends Config(
new WithNumNodes(4) ++
new WithExtMemSize(0x200000000L) ++ // 8GB
new FireSimRocketChipSingleCoreConfig)
class SupernodeSixNodeFireSimRocketChipSingleCoreConfig extends Config(
new WithNumNodes(6) ++
new WithExtMemSize(0x40000000L) ++ // 1GB
new FireSimRocketChipSingleCoreConfig)
class SupernodeEightNodeFireSimRocketChipSingleCoreConfig extends Config(
new WithNumNodes(8) ++
new WithExtMemSize(0x40000000L) ++ // 1GB
new FireSimRocketChipSingleCoreConfig)
class SupernodeFireSimRocketChipDualCoreConfig extends Config(
new WithNumNodes(4) ++
new WithExtMemSize(0x200000000L) ++ // 8GB
new FireSimRocketChipDualCoreConfig)
class SupernodeFireSimRocketChipQuadCoreConfig extends Config(
new WithNumNodes(4) ++
new WithExtMemSize(0x200000000L) ++ // 8GB
new FireSimRocketChipQuadCoreConfig)
class SupernodeFireSimRocketChipHexaCoreConfig extends Config(
new WithNumNodes(4) ++
new WithExtMemSize(0x200000000L) ++ // 8GB
new FireSimRocketChipHexaCoreConfig)
class SupernodeFireSimRocketChipOctaCoreConfig extends Config(
new WithNumNodes(4) ++
new WithExtMemSize(0x200000000L) ++ // 8GB
new FireSimRocketChipOctaCoreConfig)
new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 8L) ++ // 8 GB
new FireSimRocketConfig)

74
generators/firechip/src/main/scala/TargetTraits.scala
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@@ -1,74 +0,0 @@
package firesim.firesim
import chisel3._
import chisel3.util.Cat
import chisel3.experimental.annotate
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.util._
import freechips.rocketchip.tile.RocketTile
import freechips.rocketchip.subsystem._
import freechips.rocketchip.rocket.TracedInstruction
import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction}
import midas.targetutils.MemModelAnnotation
import boom.common.BoomTile
/* Wires out tile trace ports to the top; and wraps them in a Bundle that the
* TracerV bridge can match on.
*/
object PrintTracePort extends Field[Boolean](false)
trait HasTraceIO {
this: HasTiles =>
val module: HasTraceIOImp
// Bind all the trace nodes to a BB; we'll use this to generate the IO in the imp
val traceNexus = BundleBridgeNexus[Vec[TracedInstruction]]
val tileTraceNodes = tiles.map(tile => tile.traceNode)
tileTraceNodes foreach { traceNexus := _ }
}
trait HasTraceIOImp extends LazyModuleImp {
val outer: HasTraceIO
val traceIO = IO(Output(new TraceOutputTop(
DeclockedTracedInstruction.fromNode(outer.traceNexus.in))))
(traceIO.traces zip outer.traceNexus.in).foreach({ case (port, (tileTrace, _)) =>
port := DeclockedTracedInstruction.fromVec(tileTrace)
})
// Enabled to test TracerV trace capture
if (p(PrintTracePort)) {
val traceprint = Wire(UInt(512.W))
traceprint := Cat(traceIO.traces.map(_.reverse.asUInt))
printf("TRACEPORT: %x\n", traceprint)
}
}
trait CanHaveMultiCycleRegfileImp {
val outer: chipyard.HasBoomAndRocketTiles
outer.tiles.map {
case r: RocketTile => {
annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
}
case b: BoomTile => {
val core = b.module.core
core.iregfile match {
case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
case _ => Nil
}
if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
case _ => Nil
}
}
}
}

25
generators/firechip/src/main/scala/Targets.scala
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@@ -39,30 +39,5 @@ import FireSimValName._
* determine which driver to build.
*******************************************************************************/
class FireSimDUT(implicit p: Parameters) extends chipyard.Top
with HasTraceIO
{
override lazy val module = new FireSimModuleImp(this)
}
class FireSimModuleImp[+L <: FireSimDUT](l: L) extends chipyard.TopModule(l)
with HasTraceIOImp
with CanHaveMultiCycleRegfileImp
class FireSim(implicit p: Parameters) extends DefaultFireSimHarness
class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness
{
throw new Exception("FireSimNoNIC is deprecated. Please add WithNoNIC to your TARGET_CONFIG and set DESIGN=FireSim to build a NoNIC simulator")
}
object FireSimTypeAliases {
// Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1
type FireSimSupernode = FireSim
// Verilog blackbox integration demo
type FireSimVerilogGCD = FireSim
}
import FireSimTypeAliases._