Split IOBinders into IOBinders and Harness Binders | punch out clocks to harness for simwidgets and bridges
This commit is contained in:
Jerry Zhao
@@ -8,13 +8,13 @@ import chisel3.experimental.annotate
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import freechips.rocketchip.config.{Field, Config, Parameters}
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import freechips.rocketchip.diplomacy.{LazyModule}
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import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
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import freechips.rocketchip.amba.axi4.{AXI4Bundle}
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import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp}
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import freechips.rocketchip.tile.{RocketTile}
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import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
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import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
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import sifive.blocks.devices.uart._
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import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp}
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import icenet.CanHavePeripheryIceNICModuleImp
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import testchipip._
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import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey, NICIOvonly}
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import junctions.{NastiKey, NastiParameters}
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import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig}
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@@ -25,73 +25,116 @@ import tracegen.{TraceGenSystemModuleImp}
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import ariane.ArianeTile
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import boom.common.{BoomTile}
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import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters}
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import testchipip.{CanHaveTraceIOModuleImp}
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import barstools.iocell.chisel._
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import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder, GetSystemParameters, IOCellKey}
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import chipyard.{HasHarnessSignalReferences}
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import chipyard.harness._
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object MainMemoryConsts {
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val regionNamePrefix = "MainMemory"
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def globalName = s"${regionNamePrefix}_${NodeIdx()}"
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}
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class WithSerialBridge extends OverrideIOBinder({
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(system: CanHavePeripherySerialModuleImp) =>
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system.serial.foreach(s => SerialBridge(system.clock, s, MainMemoryConsts.globalName)(system.p)); Nil
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trait Unsupported {
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require(false, "We do not support this IOCell type")
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}
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class FireSimAnalogIOCell extends RawModule with AnalogIOCell with Unsupported
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class FireSimDigitalGPIOCell extends RawModule with DigitalGPIOCell with Unsupported
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class FireSimDigitalInIOCell extends RawModule with DigitalInIOCell { io.i := io.pad }
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class FireSimDigitalOutIOCell extends RawModule with DigitalOutIOCell { io.pad := io.o }
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case class FireSimIOCellParams() extends IOCellTypeParams {
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def analog() = Module(new FireSimAnalogIOCell)
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def gpio() = Module(new FireSimDigitalGPIOCell)
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def input() = Module(new FireSimDigitalInIOCell)
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def output() = Module(new FireSimDigitalOutIOCell)
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}
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class WithFireSimIOCellModels extends Config((site, here, up) => {
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case IOCellKey => FireSimIOCellParams()
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})
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class WithNICBridge extends OverrideIOBinder({
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(system: CanHavePeripheryIceNICModuleImp) =>
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system.net.foreach(n => NICBridge(system.clock, n)(system.p)); Nil
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class WithSerialBridge extends OverrideHarnessBinder({
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(system: CanHavePeripherySerial, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
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val clock = ports.collectFirst({case c: Clock => c})
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val p: Parameters = chipyard.iobinders.GetSystemParameters(system)
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ports.filter(_.isInstanceOf[SerialIO]).map {
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case s: SerialIO => withClockAndReset(clock.get, th.harnessReset) {
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SerialBridge(clock.get, s, MainMemoryConsts.globalName)(p)
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}
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case _ =>
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}
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Nil
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}
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})
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class WithUARTBridge extends OverrideIOBinder({
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(system: HasPeripheryUARTModuleImp) =>
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system.uart.foreach(u => UARTBridge(system.clock, u)(system.p)); Nil
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class WithNICBridge extends OverrideHarnessBinder({
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(system: CanHavePeripheryIceNICModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
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val clock = ports.collectFirst({case c: Clock => c})
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ports.map {
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case p: NICIOvonly => withClockAndReset(clock.get, th.harnessReset) { NICBridge(clock.get, p)(system.p) }
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case _ =>
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}
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Nil
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}
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})
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class WithBlockDeviceBridge extends OverrideIOBinder({
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(system: CanHavePeripheryBlockDeviceModuleImp) =>
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system.bdev.foreach(b => BlockDevBridge(system.clock, b, system.reset.toBool)(system.p)); Nil
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class WithUARTBridge extends OverrideHarnessBinder({
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(system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) =>
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ports.map { case p: UARTPortIO => UARTBridge(th.harnessClock, p)(system.p) }; Nil
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})
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class WithBlockDeviceBridge extends OverrideHarnessBinder({
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(system: CanHavePeripheryBlockDeviceModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
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val clock = ports.collectFirst({case c: Clock => c})
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ports.map {
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case p: BlockDeviceIO => BlockDevBridge(clock.get, p, th.harnessReset.toBool)(system.p)
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case _ =>
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}
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Nil
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}
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})
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class WithFASEDBridge extends OverrideIOBinder({
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(system: CanHaveMasterAXI4MemPort) => {
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class WithFASEDBridge extends OverrideHarnessBinder({
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(system: CanHaveMasterAXI4MemPort, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
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implicit val p: Parameters = GetSystemParameters(system)
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(system.mem_axi4 zip system.memAXI4Node.edges.in).foreach({ case (axi4, edge) =>
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val clock = ports.collectFirst({case c: Clock => c})
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val axi4_ports = ports.collect { case p: AXI4Bundle => p }
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(axi4_ports zip system.memAXI4Node.edges.in).map { case (axi4: AXI4Bundle, edge) =>
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val nastiKey = NastiParameters(axi4.r.bits.data.getWidth,
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axi4.ar.bits.addr.getWidth,
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axi4.ar.bits.id.getWidth)
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system match {
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case s: BaseSubsystem => FASEDBridge(s.module.clock, axi4, s.module.reset.toBool,
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case s: BaseSubsystem => FASEDBridge(clock.get, axi4, th.harnessReset.asBool,
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CompleteConfig(p(firesim.configs.MemModelKey),
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nastiKey,
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Some(AXI4EdgeSummary(edge)),
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Some(MainMemoryConsts.globalName)))
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case _ => throw new Exception("Attempting to attach FASED Bridge to misconfigured design")
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}
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})
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}
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Nil
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}
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})
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class WithTracerVBridge extends ComposeIOBinder({
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(system: CanHaveTraceIOModuleImp) =>
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system.traceIO.foreach(_.traces.map(tileTrace => TracerVBridge(tileTrace)(system.p))); Nil
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})
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class WithDromajoBridge extends ComposeIOBinder({
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(system: CanHaveTraceIOModuleImp) => {
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system.traceIO.foreach(_.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p))); Nil
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class WithTracerVBridge extends ComposeHarnessBinder({
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(system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) => {
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ports.map { case p: TraceOutputTop => p.traces.map(tileTrace =>
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withClockAndReset(tileTrace.clock, tileTrace.reset) { TracerVBridge(tileTrace)(system.p) }
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)}
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}
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})
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class WithDromajoBridge extends ComposeHarnessBinder({
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(system: CanHaveTraceIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) =>
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ports.map { case p: TraceOutputTop => p.traces.map(tileTrace => DromajoBridge(tileTrace)(system.p)) }; Nil
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})
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class WithTraceGenBridge extends OverrideIOBinder({
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(system: TraceGenSystemModuleImp) =>
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GroundTestBridge(system.clock, system.success)(system.p); Nil
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class WithTraceGenBridge extends OverrideHarnessBinder({
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(system: TraceGenSystemModuleImp, th: HasHarnessSignalReferences, ports: Seq[Data]) =>
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ports.map { case p: Bool => GroundTestBridge(th.harnessClock, p)(system.p) }; Nil
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})
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class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
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@@ -105,52 +148,25 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
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val core = b.module.core
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core.iregfile match {
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case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
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case _ => Nil
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}
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if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
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case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
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case _ => Nil
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}
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}
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case _ =>
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}
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Nil
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(Nil, Nil)
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}
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})
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class WithTiedOffSystemGPIO extends OverrideIOBinder({
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(system: HasPeripheryGPIOModuleImp) =>
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system.gpio.foreach(_.pins.foreach(_.i.ival := false.B)); Nil
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})
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class WithTiedOffSystemDebug extends OverrideIOBinder({
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(system: HasPeripheryDebugModuleImp) => {
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Debug.tieoffDebug(system.debug, system.resetctrl, Some(system.psd))(system.p)
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// tieoffDebug doesn't actually tie everything off :/
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system.debug.foreach { d =>
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d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare })
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d.dmactiveAck := DontCare
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}
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Nil
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}
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})
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class WithTiedOffSystemInterrupts extends OverrideIOBinder({
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(system: HasExtInterruptsModuleImp) =>
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system.interrupts := 0.U; Nil
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})
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// Shorthand to register all of the provided bridges above
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class WithDefaultFireSimBridges extends Config(
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new WithTiedOffSystemGPIO ++
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new WithTiedOffSystemDebug ++
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new WithTiedOffSystemInterrupts ++
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new WithSerialBridge ++
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new WithNICBridge ++
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new WithUARTBridge ++
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new WithBlockDeviceBridge ++
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new WithFASEDBridge ++
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new WithFireSimMultiCycleRegfile ++
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new WithTracerVBridge
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new WithTracerVBridge ++
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new WithFireSimIOCellModels
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)
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@@ -13,8 +13,9 @@ import freechips.rocketchip.util.{ResetCatchAndSync}
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import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock}
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import chipyard.{BuildSystem, BuildTop, HasHarnessSignalReferences, ChipyardSubsystem, ClockingSchemeKey, ChipTop}
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import chipyard.iobinders.{IOBinders}
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import chipyard._
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import chipyard.harness._
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import chipyard.iobinders._
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// Determines the number of times to instantiate the DUT in the harness.
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// Subsumes legacy supernode support
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@@ -50,7 +51,7 @@ class WithFireSimSimpleClocks extends Config((site, here, up) => {
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chiptop.implicitClockSinkNode := implicitClockSourceNode
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// Drive the diplomaticclock graph of the DigitalTop (if present)
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val simpleClockGroupSourceNode = chiptop.lSystem match {
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val simpleClockGroupSourceNode = chiptop.lazySystem match {
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case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => {
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val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
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l.asyncClockGroupsNode := n
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@@ -93,7 +94,7 @@ class WithFireSimRationalTileDomain(multiplier: Int, divisor: Int) extends Confi
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chiptop.implicitClockSinkNode := implicitClockSourceNode
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// Drive the diplomaticclock graph of the DigitalTop (if present)
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val simpleClockGroupSourceNode = chiptop.lSystem match {
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val simpleClockGroupSourceNode = chiptop.lazySystem match {
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case l: BaseSubsystem if (p(SubsystemDriveAsyncClockGroupsKey).isEmpty) => {
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val n = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
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l.asyncClockGroupsNode := n
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@@ -159,8 +160,13 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessSigna
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case AsyncClockGroupsKey => p(AsyncClockGroupsKey).copy
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})))
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val module = Module(lazyModule.module)
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require(lazyModule.harnessFunctions.size == 1, "There should only be 1 harness function to connect clock+reset")
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lazyModule.harnessFunctions.foreach(_(this))
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lazyModule match { case d: HasTestHarnessFunctions =>
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require(d.harnessFunctions.size == 1, "There should only be 1 harness function to connect clock+reset")
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d.harnessFunctions.foreach(_(this))
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ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap)
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}
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NodeIdx.increment()
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}
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}
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