wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Tile construction delayed

Browse Source
This commit is contained in:
Zitao Fang
2020-06-04 00:17:05 -07:00
parent e021f161dc
commit 0f116cb717
2 changed files with 15 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
generators/chipyard/src/main/scala/CoreManager.scala
View File

@@ -21,7 +21,7 @@ sealed trait CoreEntryBase {
def tileParamsLookup(implicit p: Parameters): Seq[TileParams] def tileParamsLookup(implicit p: Parameters): Seq[TileParams]
def updateWithFilter(view: View, p: Any => Boolean): PartialFunction[Any, Map[String, Any] => Any] def updateWithFilter(view: View, p: Any => Boolean): PartialFunction[Any, Map[String, Any] => Any]
def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => Seq[RocketCrossingParams], logicalTreeNode: LogicalTreeNode) def instantiateTile(crossingLookup: (Seq[RocketCrossingParams], Int) => Seq[RocketCrossingParams], logicalTreeNode: LogicalTreeNode)
(implicit p: Parameters, valName: ValName): Seq[(TileParams, RocketCrossingParams, BaseTile)] (implicit p: Parameters, valName: ValName): Seq[(TileParams, RocketCrossingParams, () => BaseTile)]
} }
// Implementation of third-party core entries // Implementation of third-party core entries
@@ -53,7 +53,13 @@ class CoreEntry[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTi
case (param, crossing) => ( case (param, crossing) => (
param, param,
crossing, crossing,
LazyModule(tileCtor.newInstance(param, crossing, PriorityMuxHartIdFromSeq(tileParams), logicalTreeNode, p.asInstanceOf[Parameters]).asInstanceOf[TileT]) (() => LazyModule(tileCtor.newInstance(
param,
crossing,
PriorityMuxHartIdFromSeq(tileParams),
logicalTreeNode,
p.asInstanceOf[Parameters]
).asInstanceOf[TileT]))
) )
} }
} }

9
generators/chipyard/src/main/scala/Subsystem.scala
View File

@@ -34,7 +34,9 @@ trait HasChipyardTiles extends HasTiles
val module: HasChipyardTilesModuleImp val module: HasChipyardTilesModuleImp
// Generate tiles info from the list of cores in CoreManager // Generate tiles info from the list of cores in CoreManager
val allTilesInfo: Seq[(TileParams, RocketCrossingParams, BaseTile)] = // Note: the 0-arity function is used to delay the construction of tiles to make sure that they are created
// in order
val allTilesInfo: Seq[(TileParams, RocketCrossingParams, () => BaseTile)] =
(CoreManager.cores flatMap (core => core.instantiateTile(perTileOrGlobalSetting _, logicalTreeNode))) (CoreManager.cores flatMap (core => core.instantiateTile(perTileOrGlobalSetting _, logicalTreeNode)))
// Make a tile and wire its nodes into the system, // Make a tile and wire its nodes into the system,
@@ -44,8 +46,11 @@ trait HasChipyardTiles extends HasTiles
// This MUST be performed in order of hartid // This MUST be performed in order of hartid
// There is something weird with registering tile-local interrupt controllers to the CLINT. // There is something weird with registering tile-local interrupt controllers to the CLINT.
// TODO: investigate why // TODO: investigate why
require((allTilesInfo map (info => info._1.hartId)).max == allTilesInfo.size - 1)
val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map { val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map {
case (param, crossing, tile) => { case (param, crossing, tileCtor) => {
val tile = tileCtor()
connectMasterPortsToSBus(tile, crossing) connectMasterPortsToSBus(tile, crossing)
connectSlavePortsToCBus(tile, crossing) connectSlavePortsToCBus(tile, crossing)
connectInterrupts(tile, debugOpt, clintOpt, plicOpt) connectInterrupts(tile, debugOpt, clintOpt, plicOpt)