Reorganize into bringup/simple | Bump sifive-blocks
This commit is contained in:
Abraham Gonzalez
@@ -1,11 +1,10 @@
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package chipyard.fpga.vcu118.bringup
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import chisel3._
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import chisel3.experimental.{Analog, IO}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.config.{Parameters, Field}
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import freechips.rocketchip.subsystem.{ExtMem, BaseSubsystem}
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import freechips.rocketchip.config._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.tilelink._
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import sifive.fpgashells.shell.xilinx._
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@@ -18,100 +17,31 @@ import sifive.blocks.devices.spi._
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import sifive.blocks.devices.i2c._
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import sifive.blocks.devices.gpio._
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import chipyard.harness._
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import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, CanHaveMasterTLMemPort, ChipTop}
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import chipyard.iobinders.{HasIOBinders}
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import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp}
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case object DUTFrequencyKey extends Field[Double](100.0)
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class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays {
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def dp = designParameters
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val pmod_is_sdio = p(VCU118ShellPMOD) == "SDIO"
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val jtag_location = Some(if (pmod_is_sdio) "FMC_J2" else "PMOD_J52")
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// Order matters; ddr depends on sys_clock
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val uart = Overlay(UARTOverlayKey, new UARTVCU118ShellPlacer(this, UARTShellInput()))
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val sdio = if (pmod_is_sdio) Some(Overlay(SPIOverlayKey, new SDIOVCU118ShellPlacer(this, SPIShellInput()))) else None
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val jtag = Overlay(JTAGDebugOverlayKey, new JTAGDebugVCU118ShellPlacer(this, JTAGDebugShellInput(location = jtag_location)))
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val cjtag = Overlay(cJTAGDebugOverlayKey, new cJTAGDebugVCU118ShellPlacer(this, cJTAGDebugShellInput()))
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val jtagBScan = Overlay(JTAGDebugBScanOverlayKey, new JTAGDebugBScanVCU118ShellPlacer(this, JTAGDebugBScanShellInput()))
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val fmc = Overlay(PCIeOverlayKey, new PCIeVCU118FMCShellPlacer(this, PCIeShellInput()))
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val edge = Overlay(PCIeOverlayKey, new PCIeVCU118EdgeShellPlacer(this, PCIeShellInput()))
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val topDesign = LazyModule(p(BuildTop)(dp))
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// place all clocks in the shell
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dp(ClockInputOverlayKey).foreach { _.place(ClockInputDesignInput()) }
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/*** Connect/Generate clocks ***/
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// connect to the PLL that will generate multiple clocks
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val harnessSysPLL = dp(PLLFactoryKey)()
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sys_clock.get() match {
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case Some(x : SysClockVCU118PlacedOverlay) => {
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harnessSysPLL := x.node
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}
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}
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// create and connect to the dutClock
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val dutClock = ClockSinkNode(freqMHz = dp(DUTFrequencyKey))
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val dutWrangler = LazyModule(new ResetWrangler)
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val dutGroup = ClockGroup()
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dutClock := dutWrangler.node := dutGroup := harnessSysPLL
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//InModuleBody {
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// topDesign.module match { case td: LazyModuleImp => {
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// td.clock := dutClock.in.head._1.clock
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// td.reset := dutClock.in.head._1.reset
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// }
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// }
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//}
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// connect ref clock to dummy sink node
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ref_clock.get() match {
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case Some(x : RefClockVCU118PlacedOverlay) => {
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val sink = ClockSinkNode(Seq(ClockSinkParameters()))
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sink := x.node
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}
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}
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// extra overlays
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class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118FPGATestHarness {
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/*** UART ***/
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require(dp(PeripheryUARTKey).size == 2)
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// 1st UART goes to the VCU118 dedicated UART
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// BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design
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// to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level.
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val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head)))
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dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
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// 2nd UART goes to the FMC UART
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val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput()))
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val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last)))
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dp(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2))
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val io_fmc_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last)))
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dp(UARTOverlayKey).last.place(UARTDesignInput(io_fmc_uart_bb))
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/*** SPI ***/
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require(dp(PeripherySPIKey).size == 2)
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// 1st SPI goes to the VCU118 SDIO port
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val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head)))
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val sdio_placed = dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb))
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// 2nd SPI goes to the ADI port
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val adi = Overlay(SPIOverlayKey, new BringupSPIVCU118ShellPlacer(this, SPIShellInput()))
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val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last)))
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val adi_placed = dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_spi_bb_2))
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val io_adi_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last)))
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dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_adi_spi_bb))
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/*** I2C ***/
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@@ -123,7 +53,7 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends
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/*** GPIO ***/
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val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => {
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val maxGPIOSupport = 32
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val maxGPIOSupport = 32 // max gpio per gpio chip
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val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1))
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Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names))
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})
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@@ -133,62 +63,10 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends
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placer.place(GPIODesignInput(params, io_gpio_bb(i)))
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}
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/*** DDR ***/
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val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, dutWrangler.node, harnessSysPLL))
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// connect 1 mem. channel to the FPGA DDR
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val inParams = topDesign match { case td: ChipTop =>
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td.lazySystem match { case lsys: CanHaveMasterTLMemPort =>
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lsys.memTLNode.edges.in(0)
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}
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}
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val ddrClient = TLClientNode(Seq(inParams.master))
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ddrPlaced.overlayOutput.ddr := ddrClient
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// module implementation
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override lazy val module = new BringupVCU118FPGATestHarnessImp(this)
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}
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class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences {
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val outer = _outer
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val reset = IO(Input(Bool()))
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_outer.xdc.addPackagePin(reset, "L19")
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_outer.xdc.addIOStandard(reset, "LVCMOS12")
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val reset_ibuf = Module(new IBUF)
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reset_ibuf.io.I := reset
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val sysclk: Clock = _outer.sys_clock.get() match {
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case Some(x: SysClockVCU118PlacedOverlay) => x.clock
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}
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val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk)
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_outer.sdc.addAsyncPath(Seq(powerOnReset))
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val ereset: Bool = _outer.chiplink.get() match {
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case Some(x: ChipLinkVCU118PlacedOverlay) => !x.ereset_n
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case _ => false.B
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}
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_outer.pllReset := (reset_ibuf.io.O || powerOnReset || ereset)
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// cy stuff
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val harnessClock = _outer.dutClock.in.head._1.clock
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val harnessReset = WireInit(_outer.dutClock.in.head._1.reset)
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val dutReset = harnessReset
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val success = false.B
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childClock := harnessClock
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childReset := harnessReset
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// harness binders are non-lazy
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_outer.topDesign match { case d: HasTestHarnessFunctions =>
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d.harnessFunctions.foreach(_(this))
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}
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_outer.topDesign match { case d: HasIOBinders =>
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ApplyHarnessBinders(this, d.lazySystem, d.portMap)
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}
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class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends VCU118FPGATestHarnessImp(_outer) {
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val bringupOuter = _outer
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}
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