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Reorganize into bringup/simple | Bump sifive-blocks

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This commit is contained in:
Abraham Gonzalez
2020-10-27 12:57:34 -07:00
parent 3c42e2cae7
commit 0eca51ba4d
11 changed files with 420 additions and 327 deletions
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92
fpga/src/main/scala/vcu118/bringup/Configs.scala
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@@ -1,39 +1,24 @@
package chipyard.fpga.vcu118.bringup
import math.min
import sys.process._
import freechips.rocketchip.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.config.{Config}
import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress}
import freechips.rocketchip.system._
import freechips.rocketchip.tile._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.pwm._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.i2c._
import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams}
import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import sifive.fpgashells.shell.{DesignKey}
import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
import chipyard.{BuildTop}
import chipyard.harness._
import chipyard.fpga.vcu118.{RocketVCU118Config, BoomVCU118Config}
class WithBringupPeripherals extends Config((site, here, up) => {
case PeripheryUARTKey => List(
UARTParams(address = BigInt(0x64000000L)),
UARTParams(address = BigInt(0x64003000L)))
case PeripherySPIKey => List(
SPIParams(rAddress = BigInt(0x64001000L)),
SPIParams(rAddress = BigInt(0x64004000L)))
case VCU118ShellPMOD => "SDIO"
case PeripheryI2CKey => List(
I2CParams(address = BigInt(0x64005000L)))
case PeripheryUARTKey => up(PeripheryUARTKey, site) ++ List(UARTParams(address = BigInt(0x64003000L)))
case PeripherySPIKey => up(PeripherySPIKey, site) ++ List(SPIParams(rAddress = BigInt(0x64004000L)))
case PeripheryI2CKey => List(I2CParams(address = BigInt(0x64005000L)))
case PeripheryGPIOKey => {
if (BringupGPIOs.width > 0) {
require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more)
@@ -49,60 +34,19 @@ class WithBringupPeripherals extends Config((site, here, up) => {
}
})
class SmallModifications extends Config((site, here, up) => {
case DebugModuleKey => None // disable debug module
case ExportDebug => up(ExportDebug).copy(protocols = Set(JTAG)) // don't generate HTIF DTS
case SystemBusKey => up(SystemBusKey).copy(
errorDevice = Some(DevNullParams(
Seq(AddressSet(0x3000, 0xfff)),
maxAtomic=site(XLen)/8,
maxTransfer=128,
region = RegionType.TRACKED)))
case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency =
Some(BigDecimal(site(DUTFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt))
case ControlBusKey => up(ControlBusKey, site).copy(
errorDevice = None)
case DTSTimebase => BigInt(1000000)
})
class WithBootROM extends Config((site, here, up) => {
case BootROMLocated(x) => up(BootROMLocated(x), site).map { p =>
// invoke makefile for sdboot
val freqMHz = site(DUTFrequencyKey).toInt * 1000000
val make = s"make -C fpga/src/main/resources/vcu118/sdboot PBUS_CLK=${freqMHz} bin"
require (make.! == 0, "Failed to build bootrom")
p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin")
}
})
class WithExtMemSetToDDR extends Config((site, here, up) => {
case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize))))
})
class FakeBringupConfig extends Config(
new SmallModifications ++
class WithBringupAdditions extends Config(
new WithBringupUART ++
new WithBringupSPI ++
new WithBringupI2C ++
new WithBringupGPIO ++
new WithBringupDDR ++
new WithUARTIOPassthrough ++
new WithSPIIOPassthrough ++
new WithI2CIOPassthrough ++
new WithGPIOIOPassthrough ++
new WithTLIOPassthrough ++
new WithBringupPeripherals)
class RocketBringupConfig extends Config(
new WithBringupPeripherals ++
new WithExtMemSetToDDR ++ // set the external mem port size properly
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new chipyard.config.WithNoSubsystemDrivenClocks ++
new chipyard.config.WithPeripheryBusFrequencyAsDefault ++
new WithBootROM ++ // use local bootrom
new chipyard.config.WithL2TLBs(1024) ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
//new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new chipyard.WithMulticlockCoherentBusTopology ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.system.BaseConfig)
new RocketVCU118Config)
class BoomBringupConfig extends Config(
new WithBringupPeripherals ++
new BoomVCU118Config)