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Localize clock/reset stuff to prci_ctrl_domain to improve hierarchical physical design

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This commit is contained in:
Jerry Zhao
2023-05-28 23:26:27 -07:00
parent 55d4b3807e
commit 0ec98e07d4
4 changed files with 24 additions and 27 deletions
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6
generators/chipyard/src/main/scala/clocking/ClockBinders.scala
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@@ -38,9 +38,9 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) } val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) }
val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) } val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) }
tlbus.coupleTo("clock-div-ctrl") { clockDivider.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } clockDivider.tlNode := system.prci_ctrl_bus
tlbus.coupleTo("clock-sel-ctrl") { clockSelector.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } clockSelector.tlNode := system.prci_ctrl_bus
tlbus.coupleTo("pll-ctrl") { pllCtrl.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ } pllCtrl.tlNode := system.prci_ctrl_bus
system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode

29
generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
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@@ -36,6 +36,14 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
val prci_ctrl_domain = LazyModule(new ClockSinkDomain(name=Some("chipyard-prci-control"))) val prci_ctrl_domain = LazyModule(new ClockSinkDomain(name=Some("chipyard-prci-control")))
prci_ctrl_domain.clockNode := tlbus.fixedClockNode prci_ctrl_domain.clockNode := tlbus.fixedClockNode
val prci_ctrl_bus = prci_ctrl_domain { TLXbar() }
tlbus.coupleTo("prci_ctrl") { (prci_ctrl_bus
:= TLFIFOFixer(TLFIFOFixer.all)
:= TLFragmenter(tlbus.beatBytes, tlbus.blockBytes)
:= TLBuffer()
:= _)
}
// Aggregate all the clock groups into a single node // Aggregate all the clock groups into a single node
val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node
val allClockGroupsNode = ClockGroupEphemeralNode() val allClockGroupsNode = ClockGroupEphemeralNode()
@@ -72,18 +80,23 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey)) val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey))
val clockGroupCombiner = ClockGroupCombiner() val clockGroupCombiner = ClockGroupCombiner()
val resetSynchronizer = prci_ctrl_domain { ClockGroupResetSynchronizer() } val resetSynchronizer = prci_ctrl_domain { ClockGroupResetSynchronizer() }
val tileClockGater = if (prciParams.enableTileClockGating) { prci_ctrl_domain { val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain {
TileClockGater(prciParams.baseAddress + 0x00000, tlbus) val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes))
} } else { ClockGroupEphemeralNode() } clock_gater.tlNode := prci_ctrl_bus
val tileResetSetter = if (prciParams.enableTileResetSetting) { prci_ctrl_domain { clock_gater
TileResetSetter(prciParams.baseAddress + 0x10000, tlbus, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil) } }
} } else { ClockGroupEphemeralNode() } val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain {
val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes,
tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil))
reset_setter.tlNode := prci_ctrl_bus
reset_setter
} }
(aggregator (aggregator
:= frequencySpecifier := frequencySpecifier
:= clockGroupCombiner := clockGroupCombiner
:= resetSynchronizer := resetSynchronizer
:= tileClockGater := tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp")))
:= tileResetSetter := tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp")))
:= allClockGroupsNode) := allClockGroupsNode)
} }

7
generators/chipyard/src/main/scala/clocking/TileClockGater.scala
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@@ -46,10 +46,3 @@ class TileClockGater(address: BigInt, beatBytes: Int)(implicit p: Parameters, va
} }
} }
object TileClockGater {
def apply(address: BigInt, tlbus: TLBusWrapper)(implicit p: Parameters, v: ValName) = {
val gater = LazyModule(new TileClockGater(address, tlbus.beatBytes))
tlbus.coupleTo("clock-gater") { gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
gater.clockNode
}
}

9
generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
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@@ -62,12 +62,3 @@ class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], i
} }
} }
} }
object TileResetSetter {
def apply(address: BigInt, tlbus: TLBusWrapper, tileNames: Seq[String], initResetHarts: Seq[Int])(implicit p: Parameters, v: ValName) = {
val setter = LazyModule(new TileResetSetter(address, tlbus.beatBytes, tileNames, initResetHarts))
tlbus.coupleTo("tile-reset-setter") { setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
setter.clockNode
}
}