wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Updated docs on waveform generation

Browse Source
This commit is contained in:
Mihai Tudor
2023-09-16 19:48:59 -07:00
parent a4382e650e
commit 0de940b6a0
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
docs/Simulation/Software-RTL-Simulation.rst
View File

@@ -177,8 +177,8 @@ A special target that automatically generates the waveform file for a specific t
For a Verilator simulation, this will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer. For a Verilator simulation, this will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer.
An open-source vcd-capable waveform viewer is `GTKWave <http://gtkwave.sourceforge.net/>`__. An open-source vcd-capable waveform viewer is `GTKWave <http://gtkwave.sourceforge.net/>`__.
For a VCS simulation, this will generate a vpd file (this is a proprietary waveform representation format used by Synopsys) that can be loaded to vpd-supported waveform viewers. For a VCS simulation, this will generate an fsdb file (fast signal database, a proprietary waveform representation format developed by Novas Software, later acquired by Synopsys) that can be loaded to fsdb-supported waveform viewers.
If you have Synopsys licenses, we recommend using the DVE waveform viewer. If you have Synopsys licenses, we recommend using the Verdi waveform viewer.
Visualizing Chipyard SoCs Visualizing Chipyard SoCs
-------------------------- --------------------------