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Remove comments for non-unique portions of config fragment

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This commit is contained in:
Paul Rigge
2020-05-25 14:13:15 -07:00
parent 863b3a7bc3
commit 0cdc8fe244
1 changed files with 33 additions and 33 deletions
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66
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -427,43 +427,43 @@ class RingSystemBusRocketConfig extends Config(
// DOC include end: RingSystemBusRocket // DOC include end: RingSystemBusRocket
class StreamingPassthroughRocketConfig extends Config( class StreamingPassthroughRocketConfig extends Config(
new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled passthrough new chipyard.example.WithStreamingPassthrough ++ // use top with tilelink-controlled passthrough
new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++ // use testchipip serial offchip link new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs new chipyard.config.WithL2TLBs(1024) ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system new freechips.rocketchip.system.BaseConfig)
// DOC include start: FIRRocketConfig // DOC include start: FIRRocketConfig
class FIRRocketConfig extends Config ( class FIRRocketConfig extends Config (
new chipyard.example.WithFIR ++ // use top with tilelink-controlled FIR new chipyard.example.WithFIR ++ // use top with tilelink-controlled FIR
new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++ // drive the master AXI4 memory with a SimAXIMem new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++ // use testchipip serial offchip link new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs new chipyard.config.WithL2TLBs(1024) ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system new freechips.rocketchip.system.BaseConfig)
// DOC include end: FIRRocketConfig // DOC include end: FIRRocketConfig
class SmallNVDLARocketConfig extends Config( class SmallNVDLARocketConfig extends Config(