Merge remote-tracking branch 'origin/dev' into boom-ci

generators/example/src/main/scala/Configs.scala

@@ -63,7 +63,13 @@ class GB1MemoryConfig extends Config(
   new DefaultRocketConfig)
 
 class RocketL2Config extends Config(
-  new WithInclusiveCache ++ new DefaultRocketConfig)
+  new WithInclusiveCache ++
+  new DefaultRocketConfig)
+
+class HwachaL2Config extends Config(
+  new hwacha.DefaultHwachaConfig ++
+  new WithInclusiveCache ++
+  new DefaultRocketConfig)
 
 // ------------
 // BOOM Configs
@@ -146,7 +152,8 @@ class RV32UnifiedBoomConfig extends Config(
   new boom.system.SmallRV32UnifiedBoomConfig)
 
 class BoomL2Config extends Config(
-  new WithInclusiveCache ++ new SmallDefaultBoomConfig)
+  new WithInclusiveCache ++
+  new SmallDefaultBoomConfig)
 
 // ---------------------
 // BOOM and Rocket Configs
@@ -255,4 +262,5 @@ class RV32BoomAndRocketConfig extends Config(
   new freechips.rocketchip.system.BaseConfig)
 
 class DualCoreRocketL2Config extends Config(
-  new WithInclusiveCache ++ new DualCoreRocketConfig)
+  new WithInclusiveCache ++
+  new DualCoreRocketConfig)

generators/firechip/src/main/scala/TargetMixins.scala

@@ -14,30 +14,6 @@ import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction}
 import midas.models.AXI4BundleWithEdge
 import midas.targetutils.ExcludeInstanceAsserts
 
-/** Ties together Subsystem buses in the same fashion done in the example top of Rocket Chip */
-trait HasDefaultBusConfiguration {
-  this: BaseSubsystem =>
-  // The sbus masters the cbus; here we convert TL-UH -> TL-UL
-  sbus.crossToBus(cbus, NoCrossing)
-
-  // The cbus masters the pbus; which might be clocked slower
-  cbus.crossToBus(pbus, SynchronousCrossing())
-
-  // The fbus masters the sbus; both are TL-UH or TL-C
-  FlipRendering { implicit p =>
-    sbus.crossFromBus(fbus, SynchronousCrossing())
-  }
-
-  // The sbus masters the mbus; here we convert TL-C -> TL-UH
-  private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key)
-  private val (in, out, halt) = coherenceManager(this)
-  if (nBanks != 0) {
-    sbus.coupleTo("coherence_manager") { in :*= _ }
-    mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out }
-  }
-}
-
-
 /** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges
   *  associated with each port. This drives FASED functional model sizing
   */

generators/firechip/src/main/scala/Targets.scala

@@ -31,7 +31,7 @@ import java.io.File
 *******************************************************************************/
 
 class FireSim(implicit p: Parameters) extends RocketSubsystem
-    with HasDefaultBusConfiguration
+    with HasHierarchicalBusTopology
     with CanHaveFASEDOptimizedMasterAXI4MemPort
     with HasPeripheryBootROM
     with HasNoDebug
@@ -57,7 +57,7 @@ class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l)
 
 
 class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem
-    with HasDefaultBusConfiguration
+    with HasHierarchicalBusTopology
     with CanHaveFASEDOptimizedMasterAXI4MemPort
     with HasPeripheryBootROM
     with HasNoDebug
@@ -81,7 +81,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod
 
 
 class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem
-    with HasDefaultBusConfiguration
+    with HasHierarchicalBusTopology
     with CanHaveFASEDOptimizedMasterAXI4MemPort
     with HasPeripheryBootROM
     with HasNoDebug
@@ -107,7 +107,7 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleI
     with ExcludeInvalidBoomAssertions
 
 class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem
-    with HasDefaultBusConfiguration
+    with HasHierarchicalBusTopology
     with CanHaveFASEDOptimizedMasterAXI4MemPort
     with HasPeripheryBootROM
     with HasNoDebug