From 0bfc7a94df3ac994c4c9e92fa3c5c38e2687e7dd Mon Sep 17 00:00:00 2001
From: Edward Wang <edward.c.wang@compdigitec.com>
Date: Thu, 27 Jul 2017 10:12:24 -0700
Subject: [PATCH] Make instance numbers generic for depth and width

---
 macros/src/test/scala/MacroCompilerSpec.scala |  5 +++--
 macros/src/test/scala/SimpleSplitDepth.scala  | 10 +++++-----
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/macros/src/test/scala/MacroCompilerSpec.scala b/macros/src/test/scala/MacroCompilerSpec.scala
index bac6862c..67ae9230 100644
--- a/macros/src/test/scala/MacroCompilerSpec.scala
+++ b/macros/src/test/scala/MacroCompilerSpec.scala
@@ -207,9 +207,10 @@ trait HasSimpleTestGenerator {
     writeToLib(lib, Seq(generateSRAM(lib_name, "lib", libWidth, libDepth, libMaskGran, extraPorts)))
     writeToMem(mem, Seq(generateSRAM(mem_name, "outer", memWidth, memDepth, memMaskGran)))
 
-    // Number of lib instances needed to hold the mem.
+    // Number of lib instances needed to hold the mem, in both directions.
     // Round up (e.g. 1.5 instances = effectively 2 instances)
-    val expectedInstances = math.ceil(memDepth.toFloat / libDepth).toInt
+    val depthInstances = math.ceil(memDepth.toFloat / libDepth).toInt
+    val widthInstances = math.ceil(memWidth.toFloat / libWidth).toInt
     val selectBits = mem_addr_width - lib_addr_width
 
     // Generate the header (contains the circuit statement and the target memory
diff --git a/macros/src/test/scala/SimpleSplitDepth.scala b/macros/src/test/scala/SimpleSplitDepth.scala
index 03542104..c896b449 100644
--- a/macros/src/test/scala/SimpleSplitDepth.scala
+++ b/macros/src/test/scala/SimpleSplitDepth.scala
@@ -24,7 +24,7 @@ trait HasSimpleDepthTestGenerator extends HasSimpleTestGenerator {
   """
       }
 
-      for (i <- 0 to expectedInstances - 1) {
+      for (i <- 0 to depthInstances - 1) {
         // We only support simple masks for now (either libMask == memMask or libMask == 1)
         val maskStatement = if (libHasMask) {
           if (libMaskGran.get == memMaskGran.get) {
@@ -58,18 +58,18 @@ trait HasSimpleDepthTestGenerator extends HasSimpleTestGenerator {
     node outer_dout_${i} = outer_dout_${i}_0
   """
       }
-      def generate_outer_dout_tree(i:Int, expectedInstances: Int): String = {
-        if (i > expectedInstances - 1) {
+      def generate_outer_dout_tree(i:Int, depthInstances: Int): String = {
+        if (i > depthInstances - 1) {
           "UInt<1>(\"h0\")"
         } else {
           "mux(eq(outer_addr_sel, UInt<%d>(\"h%s\")), outer_dout_%d, %s)".format(
-            selectBits, i.toHexString, i, generate_outer_dout_tree(i + 1, expectedInstances)
+            selectBits, i.toHexString, i, generate_outer_dout_tree(i + 1, depthInstances)
           )
         }
       }
       output += "  outer_dout <= "
       if (selectBits > 0) {
-        output += generate_outer_dout_tree(0, expectedInstances)
+        output += generate_outer_dout_tree(0, depthInstances)
       } else {
         output += """mux(UInt<1>("h1"), outer_dout_0, UInt<1>("h0"))"""
       }