From 0a42dd1ca1bc83d12de40ab7d5b6ebe28630bb81 Mon Sep 17 00:00:00 2001 From: Tynan McAuley Date: Wed, 3 Jan 2024 16:22:51 -0800 Subject: [PATCH] Update deprecated APIs to prepare for Chisel 5 - `IO` was moved from `chisel3.experimental` to `chisel3` - `DataMirror` was moved from `chisel3.experimental` to `chisel3.reflect` --- generators/chipyard/src/main/scala/SpikeTile.scala | 2 +- .../chipyard/src/main/scala/clocking/ClockGroupCombiner.scala | 2 +- .../chipyard/src/main/scala/clocking/TileClockGater.scala | 2 +- .../chipyard/src/main/scala/clocking/TileResetSetter.scala | 2 +- generators/chipyard/src/main/scala/iobinders/IOBinders.scala | 3 ++- 5 files changed, 6 insertions(+), 5 deletions(-) diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala index fc822c22..777b3731 100644 --- a/generators/chipyard/src/main/scala/SpikeTile.scala +++ b/generators/chipyard/src/main/scala/SpikeTile.scala @@ -2,7 +2,7 @@ package chipyard import chisel3._ import chisel3.util._ -import chisel3.experimental.{IntParam, StringParam, IO} +import chisel3.experimental.{IntParam, StringParam} import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala index e5236804..9b53cbef 100644 --- a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala +++ b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala @@ -2,7 +2,7 @@ package chipyard.clocking import chisel3._ import chisel3.util._ -import chisel3.experimental.{Analog, IO} +import chisel3.experimental.Analog import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ diff --git a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala index e299d0a9..c92e05bc 100644 --- a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala +++ b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala @@ -2,7 +2,7 @@ package chipyard.clocking import chisel3._ import chisel3.util._ -import chisel3.experimental.{Analog, IO} +import chisel3.experimental.Analog import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ diff --git a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala index 53dd36d0..88916d17 100644 --- a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala +++ b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala @@ -2,7 +2,7 @@ package chipyard.clocking import chisel3._ import chisel3.util._ -import chisel3.experimental.{Analog, IO} +import chisel3.experimental.Analog import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala index 7695be70..f67ea81f 100644 --- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala +++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala @@ -1,7 +1,8 @@ package chipyard.iobinders import chisel3._ -import chisel3.experimental.{Analog, IO, DataMirror} +import chisel3.reflect.DataMirror +import chisel3.experimental.Analog import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._