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Update harnessClk/Rst naming to buildtop | Small docs cleanup

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This commit is contained in:
abejgonzalez
2021-03-22 11:54:20 -07:00
parent 5ffad327db
commit 09ef82cabf
11 changed files with 59 additions and 59 deletions
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2
generators/chipyard/src/main/scala/Clocks.scala
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@@ -118,7 +118,7 @@ object ClockingSchemeGenerators {
}
chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => {
clock_io := th.harnessClock
clock_io := th.buildtopClock
Nil })
// return the reference frequency

38
generators/chipyard/src/main/scala/HarnessBinders.scala
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@@ -90,21 +90,21 @@ class WithUARTAdapter extends OverrideHarnessBinder({
class WithSimSPIFlashModel(rdOnly: Boolean = true) extends OverrideHarnessBinder({
(system: HasPeripherySPIFlashModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIChipIO]) => {
SimSPIFlashModel.connect(ports, th.harnessReset, rdOnly)(system.p)
SimSPIFlashModel.connect(ports, th.buildtopReset, rdOnly)(system.p)
}
})
class WithSimBlockDevice extends OverrideHarnessBinder({
(system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => {
implicit val p: Parameters = GetSystemParameters(system)
ports.map { b => SimBlockDevice.connect(b.clock, th.harnessReset.asBool, Some(b.bits)) }
ports.map { b => SimBlockDevice.connect(b.clock, th.buildtopReset.asBool, Some(b.bits)) }
}
})
class WithBlockDeviceModel extends OverrideHarnessBinder({
(system: CanHavePeripheryBlockDevice, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[BlockDeviceIO]]) => {
implicit val p: Parameters = GetSystemParameters(system)
ports.map { b => withClockAndReset(b.clock, th.harnessReset) { BlockDeviceModel.connect(Some(b.bits)) } }
ports.map { b => withClockAndReset(b.clock, th.buildtopReset) { BlockDeviceModel.connect(Some(b.bits)) } }
}
})
@@ -112,7 +112,7 @@ class WithLoopbackNIC extends OverrideHarnessBinder({
(system: CanHavePeripheryIceNIC, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => {
implicit val p: Parameters = GetSystemParameters(system)
ports.map { n =>
withClockAndReset(n.clock, th.harnessReset) {
withClockAndReset(n.clock, th.buildtopReset) {
NicLoopback.connect(Some(n.bits), p(NICKey))
}
}
@@ -122,7 +122,7 @@ class WithLoopbackNIC extends OverrideHarnessBinder({
class WithSimNetwork extends OverrideHarnessBinder({
(system: CanHavePeripheryIceNIC, th: BaseModule with HasHarnessSignalReferences, ports: Seq[ClockedIO[NICIOvonly]]) => {
implicit val p: Parameters = GetSystemParameters(system)
ports.map { n => SimNetwork.connect(Some(n.bits), n.clock, th.harnessReset.asBool) }
ports.map { n => SimNetwork.connect(Some(n.bits), n.clock, th.buildtopReset.asBool) }
}
})
@@ -152,23 +152,23 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({
ports.map({ port =>
// DOC include start: HarnessClockInstantiatorEx
withClockAndReset(th.harnessClock, th.harnessReset) {
withClockAndReset(th.buildtopClock, th.buildtopReset) {
val memOverSerialTLClockBundle = p(HarnessClockInstantiatorKey).requestClockBundle("mem_over_serial_tl_clock", memFreq)
val serial_bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
val serial_bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset)
val harnessMultiClockAXIRAM = SerialAdapter.connectHarnessMultiClockAXIRAM(
system.serdesser.get,
serial_bits,
memOverSerialTLClockBundle,
th.harnessReset)
th.buildtopReset)
// DOC include end: HarnessClockInstantiatorEx
val success = SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, th.harnessClock, th.harnessReset.asBool)
val success = SerialAdapter.connectSimSerial(harnessMultiClockAXIRAM.module.io.tsi_ser, th.buildtopClock, th.buildtopReset.asBool)
when (success) { th.success := true.B }
// connect SimDRAM from the AXI port coming from the harness multi clock axi ram
(harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) =>
val memSize = sVal.memParams.size
val lineSize = p(CacheBlockBytes)
val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toInt), edge.bundle)).suggestName("simdram")
val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), edge.bundle)).suggestName("simdram")
mem.io.axi <> axi_port.bits
mem.io.clock := axi_port.clock
mem.io.reset := axi_port.reset
@@ -244,11 +244,11 @@ class WithSimDebug extends OverrideHarnessBinder({
case d: ClockedDMIIO =>
val dtm_success = WireInit(false.B)
when (dtm_success) { th.success := true.B }
val dtm = Module(new SimDTM).connect(th.harnessClock, th.harnessReset.asBool, d, dtm_success)
val dtm = Module(new SimDTM).connect(th.buildtopClock, th.buildtopReset.asBool, d, dtm_success)
case j: JTAGIO =>
val dtm_success = WireInit(false.B)
when (dtm_success) { th.success := true.B }
val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.harnessClock, th.harnessReset.asBool, ~(th.harnessReset.asBool), dtm_success)
val jtag = Module(new SimJTAG(tickDelay=3)).connect(j, th.buildtopClock, th.buildtopReset.asBool, ~(th.buildtopReset.asBool), dtm_success)
}
}
})
@@ -282,9 +282,9 @@ class WithSerialAdapterTiedOff extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port =>
val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
withClockAndReset(th.harnessClock, th.harnessReset) {
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset)
withClockAndReset(th.buildtopClock, th.buildtopReset) {
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)
SerialAdapter.tieoff(ram.module.io.tsi_ser)
}
})
@@ -295,10 +295,10 @@ class WithSimSerial extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: HasHarnessSignalReferences, ports: Seq[ClockedIO[SerialIO]]) => {
implicit val p = chipyard.iobinders.GetSystemParameters(system)
ports.map({ port =>
val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
withClockAndReset(th.harnessClock, th.harnessReset) {
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, th.harnessClock, th.harnessReset.asBool)
val bits = SerialAdapter.asyncQueue(port, th.buildtopClock, th.buildtopReset)
withClockAndReset(th.buildtopClock, th.buildtopReset) {
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.buildtopReset)
val success = SerialAdapter.connectSimSerial(ram.module.io.tsi_ser, th.buildtopClock, th.buildtopReset.asBool)
when (success) { th.success := true.B }
}
})

12
generators/chipyard/src/main/scala/TestHarness.scala
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@@ -24,8 +24,8 @@ trait HasTestHarnessFunctions {
trait HasHarnessSignalReferences {
// clock/reset of the chiptop reference clock (can be different than the implicit harness clock/reset)
def harnessClock: Clock
def harnessReset: Reset
def buildtopClock: Clock
def buildtopReset: Reset
def dutReset: Reset
def success: Bool
}
@@ -82,8 +82,8 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign
val success = Output(Bool())
})
val harnessClock = Wire(Clock())
val harnessReset = Wire(Reset())
val buildtopClock = Wire(Clock())
val buildtopReset = Wire(Reset())
val lazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop")
val dut = Module(lazyDut.module)
@@ -96,8 +96,8 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessSign
}
val refClkBundle = p(HarnessClockInstantiatorKey).requestClockBundle("buildtop_reference_clock", freqMHz * (1000 * 1000))
harnessClock := refClkBundle.clock
harnessReset := WireInit(refClkBundle.reset)
buildtopClock := refClkBundle.clock
buildtopReset := WireInit(refClkBundle.reset)
val dutReset = refClkBundle.reset.asAsyncReset
val success = io.success