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Update harnessClk/Rst naming to buildtop | Small docs cleanup

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abejgonzalez
2021-03-22 11:54:20 -07:00
parent 5ffad327db
commit 09ef82cabf
11 changed files with 59 additions and 59 deletions
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8
fpga/src/main/scala/vcu118/TestHarness.scala
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@@ -121,13 +121,13 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod
val hReset = Wire(Reset())
hReset := _outer.dutClock.in.head._1.reset
val harnessClock = _outer.dutClock.in.head._1.clock
val harnessReset = WireInit(hReset)
val buildtopClock = _outer.dutClock.in.head._1.clock
val buildtopReset = WireInit(hReset)
val dutReset = hReset.asAsyncReset
val success = false.B
childClock := harnessClock
childReset := harnessReset
childClock := buildtopClock
childReset := buildtopReset
// harness binders are non-lazy
_outer.topDesign match { case d: HasTestHarnessFunctions =>