Update harnessClk/Rst naming to buildtop | Small docs cleanup

2021-03-22 11:54:20 -07:00
parent 5ffad327db
commit 09ef82cabf
11 changed files with 59 additions and 59 deletions
--- a/fpga/src/main/scala/arty/TestHarness.scala
+++ b/fpga/src/main/scala/arty/TestHarness.scala
@@ -27,8 +27,8 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
    val dut = Module(lazyDut.module)
  }

-  val harnessClock = clock_32MHz
-  val harnessReset = hReset
+  val buildtopClock = clock_32MHz
+  val buildtopReset = hReset
  val success = false.B

  val dutReset = dReset