Update harnessClk/Rst naming to buildtop | Small docs cleanup

fpga/src/main/scala/arty/HarnessBinders.scala

@@ -32,7 +32,7 @@ class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
   (system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
     ports.map {
       case j: JTAGIO =>
-        withClockAndReset(th.harnessClock, th.hReset) {
+        withClockAndReset(th.buildtopClock, th.hReset) {
           val io_jtag = Wire(new JTAGPins(() => new BasePin(), false)).suggestName("jtag")
 
           JTAGPinsFromPort(io_jtag, j)

fpga/src/main/scala/arty/TestHarness.scala

@@ -27,8 +27,8 @@ class ArtyFPGATestHarness(override implicit val p: Parameters) extends ArtyShell
     val dut = Module(lazyDut.module)
   }
 
-  val harnessClock = clock_32MHz
-  val harnessReset = hReset
+  val buildtopClock = clock_32MHz
+  val buildtopReset = hReset
   val success = false.B
 
   val dutReset = dReset

fpga/src/main/scala/vcu118/TestHarness.scala

@@ -121,13 +121,13 @@ class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawMod
   val hReset = Wire(Reset())
   hReset := _outer.dutClock.in.head._1.reset
 
-  val harnessClock = _outer.dutClock.in.head._1.clock
-  val harnessReset = WireInit(hReset)
+  val buildtopClock = _outer.dutClock.in.head._1.clock
+  val buildtopReset = WireInit(hReset)
   val dutReset = hReset.asAsyncReset
   val success = false.B
 
-  childClock := harnessClock
-  childReset := harnessReset
+  childClock := buildtopClock
+  childReset := buildtopReset
 
   // harness binders are non-lazy
   _outer.topDesign match { case d: HasTestHarnessFunctions =>